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1.发明申请公开(公告)号：US20070239810A1
公开(公告)日：2007-10-11
申请号：US11758767
申请日：2007-06-06
申请人： DERRICK LIN , Punit Minocha , Alexander Peleg , Yaakov Yaari , Millind Mittal , Larry Mennemeier , Benny Eitan
发明人： DERRICK LIN , Punit Minocha , Alexander Peleg , Yaakov Yaari , Millind Mittal , Larry Mennemeier , Benny Eitan
IPC分类号： G06F17/00
CPC分类号： G06F7/762 , G06F5/01 , G06F7/49994 , G06F7/76 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/30109 , G06F9/3013 , G06F9/30167 , G06F9/3885
摘要： A method and apparatus for providing, in a processor, a shift operation on a packed data element having multiple values. One embodiment of a central processing unit (CPU) includes instruction fetch logic to fetch a single-instruction-multiple-data (SIMD) shift instruction. A register stores a multiple data elements to be operated upon by the SIMD shift instruction. A barrel shifter concurrently shifts the data elements in a bit-wise manner by a variable number of bit positions in response to the SIMD shift instruction.
摘要翻译： 一种用于在处理器中提供对具有多个值的压缩数据元素进行移位操作的方法和装置。 中央处理单元（CPU）的一个实施例包括提取单指令多数据（SIMD）移位指令的指令提取逻辑。 寄存器存储通过SIMD移位指令来操作的多个数据元素。 桶形移位器响应于SIMD移位指令，同时将数据元素按比特方式移位可变数目的位位置。
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2.发明申请公开(公告)号：US20060235914A1
公开(公告)日：2006-10-19
申请号：US11454749
申请日：2006-06-15
申请人： Derrick Lin , Punit Minocha , Alexander Peleg , Yaakov Yaari , Millind Mittal , Larry Mennemeier , Benny Eitan
发明人： Derrick Lin , Punit Minocha , Alexander Peleg , Yaakov Yaari , Millind Mittal , Larry Mennemeier , Benny Eitan
IPC分类号： G06F15/00
CPC分类号： G06F7/762 , G06F5/01 , G06F7/49994 , G06F7/76 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/30109 , G06F9/3013 , G06F9/30167 , G06F9/3885
摘要： A method and apparatus for providing, in a processor, a shift operation on a packed data element having multiple values. The apparatus having multiple muxes, each of the multiple muxes having a first input, a second input, a select input and an output. Each of the multiple bits that represent a shifted packed intermediate result on a first bus is coupled to the corresponding first input. Each of the multiple bits representing a replacement bit for one of the multiple values is coupled to a corresponding second input. Each of the multiple bits driven by a correction circuit is coupled to a corresponding select input. Each output corresponds to a bit of a shifted packed result.
摘要翻译： 一种用于在处理器中提供对具有多个值的压缩数据元素进行移位操作的方法和装置。 所述装置具有多个多路复用器，所述多个多路复用器中的每一个具有第一输入，第二输入，选择输入和输出。 表示在第一总线上的移位的打包中间结果的多个比特中的每一个被耦合到对应的第一输入。 表示多个值之一的替换位的多个比特中的每一个被耦合到对应的第二输入。 由校正电路驱动的多个比特中的每一个被耦合到对应的选择输入。 每个输出对应于移位包装结果的一位。
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3.发明申请公开(公告)号：US20050219897A1
公开(公告)日：2005-10-06
申请号：US11140454
申请日：2005-05-27
申请人： Derrick Lin , Punit Minocha , Alexander Peleg , Yaakov Yaari , Millind Mittal , Larry Mennemeier , Benny Eitan
发明人： Derrick Lin , Punit Minocha , Alexander Peleg , Yaakov Yaari , Millind Mittal , Larry Mennemeier , Benny Eitan
CPC分类号： G06F7/762 , G06F5/01 , G06F7/49994 , G06F7/76 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/30109 , G06F9/3013 , G06F9/30167 , G06F9/3885
摘要： A method and apparatus for providing, in a processor, a shift operation on a packed data element having multiple values. The apparatus having multiple muxes, each of the multiple muxes having a first input, a second input, a select input and an output. Each of the multiple bits that represent a shifted packed intermediate result on a first bus is coupled to the corresponding first input. Each of the multiple bits representing a replacement bit for one of the multiple values is coupled to a corresponding second input. Each of the multiple bits driven by a correction circuit is coupled to a corresponding select input. Each output corresponds to a bit of a shifted packed result.
摘要翻译： 一种用于在处理器中提供对具有多个值的压缩数据元素进行移位操作的方法和装置。 所述装置具有多个多路复用器，所述多个多路复用器中的每一个具有第一输入，第二输入，选择输入和输出。 表示在第一总线上的移位的打包中间结果的多个比特中的每一个被耦合到对应的第一输入。 表示多个值之一的替换位的多个比特中的每一个被耦合到对应的第二输入。 由校正电路驱动的多个比特中的每一个被耦合到对应的选择输入。 每个输出对应于移位包装结果的一位。
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公开(公告)号：US6070237A
公开(公告)日：2000-05-30
申请号：US609899
申请日：1996-03-04
申请人： Alexander Peleg , Yaakov Yaari , Millind Mittal , Larry Mennemeier , Benny Eitan
发明人： Alexander Peleg , Yaakov Yaari , Millind Mittal , Larry Mennemeier , Benny Eitan
CPC分类号： G06F7/607 , G06F2207/3828
摘要： A novel processor for manipulating packed data. The packed data includes a first data element D1 and a second data element D2. Each of said data elements has a predetermined number of bits. The processor comprises a decoder, a register, and a circuit. The decoder is for decoding a control signal responsive to receiving the control signal. The register is coupled to the decoder. The register is for storing the packed data. The circuit is coupled to the decoder. The circuit is for generating a first result data element R1 and a second data element R2. The circuit is further for generating R1 to represent a total number bits set in D1, and the circuit is further for generating R2 to represent a total number bits set in D2.
摘要翻译： 一种处理打包数据的新型处理器。 打包数据包括第一数据元素D1和第二数据元素D2。 每个所述数据元素具有预定数量的位。 处理器包括解码器，寄存器和电路。 解码器用于响应于接收控制信号来解码控制信号。 寄存器耦合到解码器。 寄存器用于存储打包数据。 电路耦合到解码器。 电路用于生成第一结果数据元素R1和第二数据元素R2。 电路还用于产生R1以表示在D1中设置的总数位，并且该电路还用于生成R2以表示在D2中设置的总数位。
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公开(公告)号：US20060236076A1
公开(公告)日：2006-10-19
申请号：US11451906
申请日：2006-06-12
申请人： Alexander Peleg , Yaakov Yaari , Millind Mittal , Larry Mennemeier , Benny Eitan
发明人： Alexander Peleg , Yaakov Yaari , Millind Mittal , Larry Mennemeier , Benny Eitan
IPC分类号： G06F15/00
CPC分类号： G06F9/30036 , G06F7/49921 , G06F9/30025 , G06F9/30032 , G06F9/30109 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/30167 , G06F9/30181 , G06F9/30192 , G06F9/30196
摘要： An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to pack the packed data responsive to a pack instruction received by the decoder. A first packed data element and a second packed data element are received from the first source register. A third packed data element and a fourth packed data element are received from the second source register. The circuit packs packing a portion of each of the packed data elements into a destination register resulting with the portion from second packed data element adjacent to the portion from the first packed data element, and the portion from the fourth packed data element adjacent to the portion from the third packed data element.
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6.发明申请Processor with instructions that operate on different data types stored in the same single logical register file 审中-公开处理器具有对存储在同一个逻辑寄存器文件中的不同数据类型进行操作的指令公开(公告)号：US20050038977A1
公开(公告)日：2005-02-17
申请号：US10940268
申请日：2004-09-13
申请人： Andrew Glew , Larry Mennemeier , Alexander Peleg , David Bistry , Millind Mittal , Carole Dulong , Eiichi Kowashi , Benny Eitan , Derrick Lin , Ramamohan Vakkalagadda
发明人： Andrew Glew , Larry Mennemeier , Alexander Peleg , David Bistry , Millind Mittal , Carole Dulong , Eiichi Kowashi , Benny Eitan , Derrick Lin , Ramamohan Vakkalagadda
CPC分类号： G06F9/3017 , G06F9/30036 , G06F9/30105 , G06F9/30109 , G06F9/30112 , G06F9/30134 , G06F9/30189 , G06F9/384 , G06F9/462
摘要： A processor with instructions to operate on different data types stored in a single logical register file. According to one embodiment of the invention, a processor includes a number of physical registers, a memory unit, and a decode/execution unit. The memory unit is to make the number of physical registers appear to software as a single software-visible register file. The decode/execution unit is to execute on the contents of the single software-visible register file instructions of a first instruction type and of a second instruction type, wherein the single software-visible register file is to be operated as a flat register file during execution of instructions of the second instruction type and as a stack referenced register file during execution of instructions of the first instruction type.
摘要翻译： 具有对存储在单个逻辑寄存器文件中的不同数据类型进行操作的指令的处理器。 根据本发明的一个实施例，处理器包括多个物理寄存器，存储器单元和解码/执行单元。 存储单元是将物理寄存器的数量作为单个软件可见的寄存器文件显示在软件上。 解码/执行单元执行第一指令类型和第二指令类型的单个软件可见寄存器文件指令的内容，其中单个软件可见寄存器文件将作为平坦寄存器文件操作 在执行第一指令类型的指令期间执行第二指令类型的指令和作为堆栈引用的寄存器堆栈。
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7.发明授权Packing signed word elements from two source registers to saturated signed byte elements in destination register 失效将来自两个源寄存器的符号字元素包装到目标寄存器中的饱和有符号字节元素公开(公告)号：US08639914B2
公开(公告)日：2014-01-28
申请号：US13730831
申请日：2012-12-29
IPC分类号： G06F15/80
CPC分类号： G06F9/30036 , G06F7/49921 , G06F9/30025 , G06F9/30032 , G06F9/30109 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/30167 , G06F9/30181 , G06F9/30192 , G06F9/30196
摘要： An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element.
摘要翻译： 一种装置包括指令解码器，第一和第二源寄存器以及耦合到解码器的电路，用于从源寄存器接收压缩数据，并根据解码器接收到的解包指令对打包数据进行解包。 从第一源寄存器接收第一打包数据元素和第三打包数据元素。 从第二源寄存器接收第二打包数据元素和第四打包数据元素。 所述电路将打包的数据元素复制到目的地寄存器中，其中与第一打包数据元素相邻的第二打包数据元素，与第二打包数据元素相邻的第三打包数据元素以及与第三打包数据元素相邻的第四打包数据元素 数据元素。
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公开(公告)号：US20130124833A1
公开(公告)日：2013-05-16
申请号：US13730846
申请日：2012-12-29
IPC分类号： G06F9/30
CPC分类号： G06F9/30036 , G06F7/49921 , G06F9/30025 , G06F9/30032 , G06F9/30109 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/30167 , G06F9/30181 , G06F9/30192 , G06F9/30196
摘要： An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element.
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公开(公告)号：US20130117540A1
公开(公告)日：2013-05-09
申请号：US13730832
申请日：2012-12-29
IPC分类号： G06F9/30
CPC分类号： G06F9/30036 , G06F7/49921 , G06F9/30025 , G06F9/30032 , G06F9/30109 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/30167 , G06F9/30181 , G06F9/30192 , G06F9/30196
摘要： An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element.
摘要翻译： 一种装置包括指令解码器，第一和第二源寄存器以及耦合到解码器的电路，用于从源寄存器接收压缩数据，并根据解码器接收到的解包指令对打包数据进行解包。 从第一源寄存器接收第一打包数据元素和第三打包数据元素。 从第二源寄存器接收第二打包数据元素和第四打包数据元素。 所述电路将打包的数据元素复制到目的地寄存器中，其中与第一打包数据元素相邻的第二打包数据元素，与第二打包数据元素相邻的第三打包数据元素以及与第三打包数据元素相邻的第四打包数据元素 数据元素。
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公开(公告)号：US5677862A
公开(公告)日：1997-10-14
申请号：US630876
申请日：1996-04-02
CPC分类号： G06F7/53 , G06F9/30014 , G06F9/30025 , G06F9/30036 , G06F9/3885 , G06F2207/3828 , G06F7/49921
摘要： A processor. The processor includes a decoder being coupled to receive a control signal. The control signal has a first source address, a second source address, a destination address, and an operation field. The first source address corresponds to a first location. The second source address corresponds to a second location. The destination address corresponds to a third location. The operation field indicates that a type of packed data multiply operation is to be performed. The processor further includes a circuit being coupled to the decoder. The circuit is for multiplying a first packed data being stored at the first location with a second packed data being stored at the second location. The circuit is further for communicating a corresponding result packed data to the third location.
摘要翻译： 处理器 处理器包括被耦合以接收控制信号的解码器。 控制信号具有第一源地址，第二源地址，目的地地址和操作字段。 第一个源地址对应于第一个位置。 第二源地址对应于第二位置。 目的地址对应于第三个位置。 操作字段指示要执行一种打包数据乘法运算。 处理器还包括耦合到解码器的电路。 该电路用于将在第一位置处存储的第一打包数据与存储在第二位置处的第二打包数据相乘。 电路还用于将相应的结果打包数据传送到第三位置。
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