公开(公告)号：US07883953B2

公开(公告)日：2011-02-08

申请号：US12242078

申请日：2008-09-30

申请人： Da Zhang ,  Voon-Yew Thean ,  Christopher V. Baiocco ,  Jie Chen ,  Weipeng Li ,  Young Way Teh ,  Jin Wallner

发明人： Da Zhang ,  Voon-Yew Thean ,  Christopher V. Baiocco ,  Jie Chen ,  Weipeng Li ,  Young Way Teh ,  Jin Wallner

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L29/045 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/7843

摘要： A semiconductor process and apparatus includes forming channel orientation CMOS transistors (24, 34) with enhanced hole mobility in the NMOS channel region and reduced channel defectivity in the PMOS region by depositing a first tensile etch stop layer (51) over the PMOS and NMOS gate structures, etching the tensile etch stop layer (51) to form tensile sidewall spacers (62) on the exposed gate sidewalls, and then depositing a second hydrogen rich compressive or neutral etch stop layer (72) over the NMOS and PMOS gate structures (26, 36) and the tensile sidewall spacers (62). In other embodiments, a first hydrogen-rich etch stop layer (81) is deposited and etched to form sidewall spacers (92) on the exposed gate sidewalls, and then a second tensile etch stop layer (94) is deposited over the NMOS and PMOS gate structures (26, 36) and the sidewall spacers (92).

摘要翻译： 一种半导体工艺和设备包括在NMOS沟道区中形成具有增强的空穴迁移率的<100>沟道定向CMOS晶体管（24,34），并且通过在PMOS区上沉积第一拉伸蚀刻停止层（51），减小PMOS区域中的沟道缺陷率 蚀刻所述拉伸蚀刻停止层（51）以在所述暴露的栅极侧壁上形成拉伸侧壁间隔物（62），然后在所述NMOS和PMOS栅极上沉积第二富氢压缩或中性蚀刻停止层（72） 结构（26,36）和拉伸侧壁间隔物（62）。 在其它实施例中，沉积并蚀刻第一富氢蚀刻停止层（81）以在暴露的栅极侧壁上形成侧壁间隔物（92），然后在NMOS和PMOS上沉积第二拉伸蚀刻停止层（94） 栅极结构（26,36）和侧壁间隔物（92）。

公开(公告)号：US20100078687A1

公开(公告)日：2010-04-01

申请号：US12242078

申请日：2008-09-30

申请人： Da Zhang ,  Voon-Yew Thean ,  Christopher V. Baiocco ,  Jie Chen ,  Weipeng Li ,  Young Way Teh ,  Jin Wallner

发明人： Da Zhang ,  Voon-Yew Thean ,  Christopher V. Baiocco ,  Jie Chen ,  Weipeng Li ,  Young Way Teh ,  Jin Wallner

IPC分类号： H01L21/8238 ,  H01L29/04

CPC分类号： H01L21/823807 ,  H01L29/045 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/7843

摘要： A semiconductor process and apparatus includes forming channel orientation CMOS transistors (24, 34) with enhanced hole mobility in the NMOS channel region and reduced channel defectivity in the PMOS region by depositing a first tensile etch stop layer (51) over the PMOS and NMOS gate structures, etching the tensile etch stop layer (51) to form tensile sidewall spacers (62) on the exposed gate sidewalls, and then depositing a second hydrogen rich compressive or neutral etch stop layer (72) over the NMOS and PMOS gate structures (26, 36) and the tensile sidewall spacers (62). In other embodiments, a first hydrogen-rich etch stop layer (81) is deposited and etched to form sidewall spacers (92) on the exposed gate sidewalls, and then a second tensile etch stop layer (94) is deposited over the NMOS and PMOS gate structures (26, 36) and the sidewall spacers (92).

摘要翻译： 一种半导体工艺和设备包括在NMOS沟道区中形成具有增强的空穴迁移率的<100>沟道定向CMOS晶体管（24,34），并且通过在PMOS区上沉积第一拉伸蚀刻停止层（51），减小PMOS区域中的沟道缺陷率 蚀刻所述拉伸蚀刻停止层（51）以在所述暴露的栅极侧壁上形成拉伸侧壁间隔物（62），然后在所述NMOS和PMOS栅极上沉积第二富氢压缩或中性蚀刻停止层（72） 结构（26,36）和拉伸侧壁间隔物（62）。 在其它实施例中，沉积并蚀刻第一富氢蚀刻停止层（81）以在暴露的栅极侧壁上形成侧壁间隔物（92），然后在NMOS和PMOS上沉积第二拉伸蚀刻停止层（94） 栅极结构（26,36）和侧壁间隔物（92）。

公开(公告)号：US08124534B2

公开(公告)日：2012-02-28

申请号：US12177690

申请日：2008-07-22

申请人： Jin Wallner ,  Thomas A. Wallner ,  Ying Zhang

发明人： Jin Wallner ,  Thomas A. Wallner ,  Ying Zhang

IPC分类号： H01L21/302

CPC分类号： H01L21/31116 ,  H01L21/32137 ,  H01L21/32139 ,  H01L21/76816

摘要： A process including forming a silicon layer over a semiconductor wafer having features thereon and then selectively ion implanting in the silicon layer to form ion implanted regions. The step of selectively ion implanting is repeated as many times as necessary to obtain a predetermined number and density of features. Thereafter, the silicon layer is etched to form openings in the silicon layer that were formerly occupied by the ion implanted regions. The opened areas in the silicon layer form a mask for further processing of the semiconductor wafer.

摘要翻译： 一种方法，包括在其上具有特征的半导体晶片上形成硅层，然后选择性地离子注入到硅层中以形成离子注入区域。 选择性离子注入的步骤根据需要重复多次，以获得预定数量和特征密度。 此后，蚀刻硅层以在硅层中形成先前由离子注入区域占据的开口。 硅层中的开放区域形成用于进一步处理半导体晶片的掩模。

公开(公告)号：US20100022088A1

公开(公告)日：2010-01-28

申请号：US12177690

申请日：2008-07-22

申请人： Jin Wallner ,  Thomas A. Wallner ,  Ying Zhang

发明人： Jin Wallner ,  Thomas A. Wallner ,  Ying Zhang

IPC分类号： H01L21/311 ,  H01L21/3115 ,  H01L21/3065

CPC分类号： H01L21/31116 ,  H01L21/32137 ,  H01L21/32139 ,  H01L21/76816

摘要： A process including forming a silicon layer over a semiconductor wafer having features thereon and then selectively ion implanting in the silicon layer to form ion implanted regions. The step of selectively ion implanting is repeated as many times as necessary to obtain a predetermined number and density of features. Thereafter, the silicon layer is etched to form openings in the silicon layer that were formerly occupied by the ion implanted regions. The opened areas in the silicon layer form a mask for further processing of the semiconductor wafer.

摘要翻译： 一种方法，包括在其上具有特征的半导体晶片上形成硅层，然后选择性地离子注入到硅层中以形成离子注入区域。 选择性离子注入的步骤根据需要重复多次，以获得预定数量和特征密度。 此后，蚀刻硅层以在硅层中形成先前由离子注入区域占据的开口。 硅层中的开放区域形成用于进一步处理半导体晶片的掩模。