Hybrid gate process for fabricating finfet device
    3.
    发明授权
    Hybrid gate process for fabricating finfet device 有权
    用于制造finfet器件的混合栅极工艺

    公开(公告)号:US08609495B2

    公开(公告)日:2013-12-17

    申请号:US12756662

    申请日:2010-04-08

    IPC分类号: H01L27/092 H01L21/8238

    摘要: Provided is a method of fabricating a semiconductor device that includes forming first and second fins over first and second regions of a substrate, forming first and second gate structures over the first and second fins, the first and second gate structures including first and second poly gates, forming an inter-level dielectric (ILD) over the substrate, performing a chemical mechanical polishing on the ILD to expose the first and second poly gates, forming a mask to protect the first poly gate of the first gate structure, removing the second poly gate thereby forming a first trench, removing the mask, partially removing the first poly gate thereby forming a second trench, forming a work function metal layer partially filling the first and second trenches, forming a fill metal layer filling a remainder of the first and second trenches, and removing the metal layers outside the first and second trenches.

    摘要翻译: 提供一种制造半导体器件的方法,该半导体器件包括在衬底的第一和第二区域上形成第一和第二鳍片,在第一和第二鳍片上形成第一和第二栅极结构,第一和第二栅极结构包括第一和第二多晶硅栅极 ,在所述衬底上形成层间电介质(ILD),在所述ILD上进行化学机械抛光以暴露所述第一和第二多晶硅栅极,形成掩模以保护所述第一栅极结构的所述第一多晶硅栅极, 从而形成第一沟槽,去除掩模,部分地移除第一多晶硅栅极,从而形成第二沟槽,形成部分填充第一和第二沟槽的功函数金属层,形成填充第一和第二沟槽的剩余部分的填充金属层 沟槽,并且去除第一和第二沟槽外的金属层。

    Hybrid Gate Process For Fabricating Finfet Device
    4.
    发明申请
    Hybrid Gate Process For Fabricating Finfet Device 有权
    用于制造Finfet设备的混合门过程

    公开(公告)号:US20110248348A1

    公开(公告)日:2011-10-13

    申请号:US12756662

    申请日:2010-04-08

    IPC分类号: H01L27/092 H01L21/8238

    摘要: Provided is a method of fabricating a semiconductor device that includes forming first and second fins over first and second regions of a substrate, forming first and second gate structures over the first and second fins, the first and second gate structures including first and second poly gates, forming an inter-level dielectric (ILD) over the substrate, performing a chemical mechanical polishing on the ILD to expose the first and second poly gates, forming a mask to protect the first poly gate of the first gate structure, removing the second poly gate thereby forming a first trench, removing the mask, partially removing the first poly gate thereby forming a second trench, forming a work function metal layer partially filling the first and second trenches, forming a fill metal layer filling a remainder of the first and second trenches, and removing the metal layers outside the first and second trenches.

    摘要翻译: 提供一种制造半导体器件的方法,该半导体器件包括在衬底的第一和第二区域上形成第一和第二鳍片,在第一和第二鳍片上形成第一和第二栅极结构,第一和第二栅极结构包括第一和第二多晶硅栅极 ,在所述衬底上形成层间电介质(ILD),在所述ILD上进行化学机械抛光以暴露所述第一和第二多晶硅栅极,形成掩模以保护所述第一栅极结构的所述第一多晶硅栅极, 从而形成第一沟槽,去除掩模,部分地移除第一多晶硅栅极,从而形成第二沟槽,形成部分填充第一和第二沟槽的功函数金属层,形成填充第一和第二沟槽的剩余部分的填充金属层 沟槽,并且去除第一和第二沟槽外的金属层。