公开(公告)号：US12111711B2

公开(公告)日：2024-10-08

申请号：US17402927

申请日：2021-08-16

Applicant: Daedalus Prime LLC

Inventor： Travis T. Schluessler ,  Russell J. Fenger

IPC: G06F1/32 ,  G06F1/20 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/3287 ,  G06F1/329 ,  G06F9/50

CPC classification number: G06F1/3206 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/3253 ,  G06F1/3287 ,  G06F1/329 ,  G06F9/5094 ,  G06F9/50 ,  Y02D10/00

Abstract: An apparatus, method and system is described herein for efficiently balancing performance and power between processing elements based on measured workloads. If a workload of a processing element indicates that it is a bottleneck, then its performance may be increased. However, if a platform or integrated circuit including the processing element is already operating at a power or thermal limit, the increase in performance is counterbalanced by a reduction or cap in another processing elements performance to maintain compliance with the power or thermal limit. As a result, bottlenecks are identified and alleviated by balancing power allocation, even when multiple processing elements are operating at a power or thermal limit.

公开(公告)号：US20250013281A1

公开(公告)日：2025-01-09

申请号：US18890669

申请日：2024-09-19

Applicant: Daedalus Prime LLC

Inventor： Travis T. Schluessler ,  Russell J. Fenger

IPC: G06F1/3206 ,  G06F1/20 ,  G06F1/3203 ,  G06F1/3234 ,  G06F1/3287 ,  G06F1/329 ,  G06F9/50

Abstract: An apparatus, method and system is described herein for efficiently balancing performance and power between processing elements based on measured workloads. If a workload of a processing element indicates that it is a bottleneck, then its performance may be increased. However, if a platform or integrated circuit including the processing element is already operating at a power or thermal limit, the increase in performance is counterbalanced by a reduction or cap in another processing elements performance to maintain compliance with the power or thermal limit. As a result, bottlenecks are identified and alleviated by balancing power allocation, even when multiple processing elements are operating at a power or thermal limit.