公开(公告)号：US11508813B2

公开(公告)日：2022-11-22

申请号：US17025077

申请日：2020-09-18

申请人： Daedalus Prime LLC

发明人： Glenn A. Glass ,  Anand S. Murthy

IPC分类号： H01L29/06 ,  H01L21/285 ,  H01L29/165 ,  H01L29/45 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L21/768 ,  H01L29/167 ,  H01L21/02 ,  H01L29/08 ,  H01L29/36 ,  H01L27/092 ,  H01L23/535 ,  H01L29/417 ,  H01L21/3215 ,  H01L29/778

摘要： Techniques are disclosed for forming column IV transistor devices having source/drain regions with high concentrations of germanium, and exhibiting reduced parasitic resistance relative to conventional devices. In some example embodiments, the source/drain regions each includes a thin p-type silicon or germanium or SiGe deposition with the remainder of the source/drain material deposition being p-type germanium or a germanium alloy (e.g., germanium:tin or other suitable strain inducer, and having a germanium content of at least 80 atomic % and 20 atomic % or less other components). In some cases, evidence of strain relaxation may be observed in the germanium rich cap layer, including misfit dislocations and/or threading dislocations and/or twins. Numerous transistor configurations can be used, including both planar and non-planar transistor structures (e.g., FinFETs and nanowire transistors), as well as strained and unstrained channel structures.

公开(公告)号：US12111711B2

公开(公告)日：2024-10-08

申请号：US17402927

申请日：2021-08-16

申请人： Daedalus Prime LLC

发明人： Travis T. Schluessler ,  Russell J. Fenger

IPC分类号： G06F1/32 ,  G06F1/20 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/3287 ,  G06F1/329 ,  G06F9/50

CPC分类号： G06F1/3206 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/3253 ,  G06F1/3287 ,  G06F1/329 ,  G06F9/5094 ,  G06F9/50 ,  Y02D10/00

摘要： An apparatus, method and system is described herein for efficiently balancing performance and power between processing elements based on measured workloads. If a workload of a processing element indicates that it is a bottleneck, then its performance may be increased. However, if a platform or integrated circuit including the processing element is already operating at a power or thermal limit, the increase in performance is counterbalanced by a reduction or cap in another processing elements performance to maintain compliance with the power or thermal limit. As a result, bottlenecks are identified and alleviated by balancing power allocation, even when multiple processing elements are operating at a power or thermal limit.

公开(公告)号：US20240192751A1

公开(公告)日：2024-06-13

申请号：US18384180

申请日：2023-10-26

申请人： Daedalus Prime LLC

发明人： Ryan D. Wells ,  Itai Feit ,  Doron Rajwan ,  Nadav Shulman ,  Zeev Offen ,  Inder M. Sodhi

IPC分类号： G06F1/28 ,  G06F1/26 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3296 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0897

CPC分类号： G06F1/28 ,  G06F1/266 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/26 ,  G06F1/3296 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0897 ,  Y02D10/00

摘要： In an embodiment, a processor includes a core domain with a plurality of cores and a power controller having a first logic to receive a first request to increase an operating voltage of a first core of the core domain to a second voltage, to instruct a voltage regulator to increase the operating voltage to an interim voltage, and to thereafter instruct the voltage regulator to increase the operating voltage to the second voltage. Other embodiments are described and claimed.

公开(公告)号：US11822409B2

公开(公告)日：2023-11-21

申请号：US17969408

申请日：2022-11-01

申请人： Daedalus Prime LLC

发明人： Ryan D. Wells ,  Itai Feit ,  Doron Rajwan ,  Nadav Shulman ,  Zeev Offen ,  Inder M. Sodhi

IPC分类号： G06F1/28 ,  G06F1/324 ,  G06F1/3206 ,  G06F1/26 ,  G06F1/3296 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0897

CPC分类号： G06F1/28 ,  G06F1/266 ,  G06F1/324 ,  G06F1/3206 ,  G06F1/26 ,  G06F1/3296 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0897 ,  Y02D10/00

摘要： In an embodiment, a processor includes a core domain with a plurality of cores and a power controller having a first logic to receive a first request to increase an operating voltage of a first core of the core domain to a second voltage, to instruct a voltage regulator to increase the operating voltage to an interim voltage, and to thereafter instruct the voltage regulator to increase the operating voltage to the second voltage. Other embodiments are described and claimed.

公开(公告)号：US20230197848A1

公开(公告)日：2023-06-22

申请号：US18112063

申请日：2023-02-21

申请人： Daedalus Prime LLC

发明人： Michael Jackson ,  Anand Murthy ,  Glenn Glass ,  Saurabh Morarka ,  Chandra Mohapatra

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/06 ,  H01L29/32

CPC分类号： H01L29/7848 ,  H01L29/66568 ,  H01L29/1054 ,  H01L29/0673 ,  H01L29/32 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/1033 ,  H01L29/165

摘要： Methods of forming a strained channel device utilizing dislocations disposed in source/drain structures are described. Those methods and structures may include forming a thin silicon germanium material in a source/drain opening of a device comprising silicon, wherein multiple dislocations are formed in the silicon germanium material. A source/drain material may be formed on the thin silicon germanium material, wherein the dislocations induce a tensile strain in a channel region of the device.

公开(公告)号：US20230178594A1

公开(公告)日：2023-06-08

申请号：US18068826

申请日：2022-12-20

申请人： Daedalus Prime LLC

发明人： Milton Clair Webb ,  Mark Bohr ,  Tahir Ghani ,  Szuya S. Liao

IPC分类号： H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/768 ,  H01L21/8238 ,  H01L23/535 ,  H01L27/092 ,  H01L29/417

CPC分类号： H01L29/0649 ,  H01L21/76895 ,  H01L21/823821 ,  H01L23/535 ,  H01L27/0924 ,  H01L29/785 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795 ,  H01L21/823481 ,  H01L21/823842

摘要： Self-aligned gate edge and local interconnect structures and methods of fabricating self-aligned gate edge and local interconnect structures are described. In an example, a semiconductor structure includes a semiconductor fin disposed above a substrate and having a length in a first direction. A gate structure is disposed over the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate edge isolation structures is centered with the semiconductor fin. A first of the pair of gate edge isolation structures is disposed directly adjacent to the first end of the gate structure, and a second of the pair of gate edge isolation structures is disposed directly adjacent to the second end of the gate structure.

公开(公告)号：US20230170388A1

公开(公告)日：2023-06-01

申请号：US18095720

申请日：2023-01-11

申请人： Daedalus Prime LLC

发明人： Stephen M. Cea ,  Roza Kotlyar ,  Harold W. Kennel ,  Anand S. Murthy ,  Glenn A. Glass ,  Kelin J. Kuhn ,  Tahir Ghani

IPC分类号： H01L29/10 ,  H01L29/66 ,  H01L29/778 ,  H01L29/165 ,  H01L21/84 ,  H01L27/12 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/161

CPC分类号： H01L29/1054 ,  H01L29/66431 ,  H01L29/7781 ,  H01L29/7782 ,  H01L29/165 ,  H01L21/845 ,  H01L29/66818 ,  H01L27/1211 ,  H01L29/7842 ,  H01L29/7848 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/161 ,  H01L29/045

摘要： Techniques and methods related to strained NMOS and PMOS devices without relaxed substrates, systems incorporating such semiconductor devices, and methods therefor may include a semiconductor device that may have both n-type and p-type semiconductor bodies. Both types of semiconductor bodies may be formed from an initially strained semiconductor material such as silicon germanium. A silicon cladding layer may then be provided at least over or on the n-type semiconductor body. In one example, a lower portion of the semiconductor bodies is formed by a Si extension of the wafer or substrate. By one approach, an upper portion of the semiconductor bodies, formed of the strained SiGe, may be formed by blanket depositing the strained SiGe layer on the Si wafer, and then etching through the SiGe layer and into the Si wafer to form the semiconductor bodies or fins with the lower and upper portions.

公开(公告)号：US20230006063A1

公开(公告)日：2023-01-05

申请号：US17941814

申请日：2022-09-09

申请人： Daedalus Prime LLC

发明人： Michael Jackson ,  Anand Murthy ,  Glenn Glass ,  Saurabh Morarka ,  Chandra Mohapatra

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/06 ,  H01L29/32

摘要： Methods of forming a strained channel device utilizing dislocations disposed in source/drain structures are described. Those methods and structures may include forming a thin silicon germanium material in a source/drain opening of a device comprising silicon, wherein multiple dislocations are formed in the silicon germanium material. A source/drain material may be formed on the thin silicon germanium material, wherein the dislocations induce a tensile strain in a channel region of the device.

公开(公告)号：US11507167B2

公开(公告)日：2022-11-22

申请号：US17645202

申请日：2021-12-20

申请人： Daedalus Prime LLC

发明人： Ryan D. Wells ,  Itai Feit ,  Doron Rajwan ,  Nadav Shulman ,  Zeev Offen ,  Inder M. Sodhi

IPC分类号： G06F1/28 ,  G06F1/324 ,  G06F1/3206 ,  G06F1/26 ,  G06F1/3296 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0897

摘要： In an embodiment, a processor includes a core domain with a plurality of cores and a power controller having a first logic to receive a first request to increase an operating voltage of a first core of the core domain to a second voltage, to instruct a voltage regulator to increase the operating voltage to an interim voltage, and to thereafter instruct the voltage regulator to increase the operating voltage to the second voltage. Other embodiments are described and claimed.

公开(公告)号：US11610995B2

公开(公告)日：2023-03-21

申请号：US17941814

申请日：2022-09-09

申请人： Daedalus Prime LLC

发明人： Michael Jackson ,  Anand Murthy ,  Glenn Glass ,  Saurabh Morarka ,  Chandra Mohapatra

IPC分类号： H01L29/76 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/06 ,  H01L29/32 ,  H01L29/165

摘要： Methods of forming a strained channel device utilizing dislocations disposed in source/drain structures are described. Those methods and structures may include forming a thin silicon germanium material in a source/drain opening of a device comprising silicon, wherein multiple dislocations are formed in the silicon germanium material. A source/drain material may be formed on the thin silicon germanium material, wherein the dislocations induce a tensile strain in a channel region of the device.