公开(公告)号：US07608889B2

公开(公告)日：2009-10-27

申请号：US11864278

申请日：2007-09-28

申请人： Dah-Chuen Ho ,  Chien-Shao Tang ,  Zhe-Yi Wang ,  Yu-Chang Jong

发明人： Dah-Chuen Ho ,  Chien-Shao Tang ,  Zhe-Yi Wang ,  Yu-Chang Jong

IPC分类号： H01L29/78

CPC分类号： H01L29/7835 ,  H01L29/0653 ,  H01L29/4933 ,  H01L29/66659

摘要： A lateral diffusion metal-oxide-semiconductor (LDMOS) structure comprises a gate, a source, a drain and a shallow trench isolation. The shallow trench isolation is formed between the drain and the gate to withstand high voltages, applied to the drain, and is associated with the semiconductor substrate to form a recess. As such, the surface of the shallow trench isolation is lower than the surface of the semiconductor substrate. Optionally, the surface of the shallow trench isolation is lower than the surface of the semiconductor substrate by 300-1500 angstroms.

摘要翻译： 横向扩散金属氧化物半导体（LDMOS）结构包括栅极，源极，漏极和浅沟槽隔离。 浅沟槽隔离形成在漏极和栅极之间以承受施加到漏极上的高电压，并且与半导体衬底相关联以形成凹部。 因此，浅沟槽隔离的表面低于半导体衬底的表面。 可选地，浅沟槽隔离的表面比半导体衬底的表面低300-1500埃。

公开(公告)号：US20090294865A1

公开(公告)日：2009-12-03

申请号：US12127629

申请日：2008-05-27

申请人： Chien-Shao Tang ,  Dah-Chuen Ho ,  Yu-Chang Jong ,  Zhe-Yi Wang ,  Yuh-Hwa Chang ,  Yogendra Yadav

发明人： Chien-Shao Tang ,  Dah-Chuen Ho ,  Yu-Chang Jong ,  Zhe-Yi Wang ,  Yuh-Hwa Chang ,  Yogendra Yadav

IPC分类号： H01L27/06

CPC分类号： H01L27/0629 ,  H01L29/0619 ,  H01L29/0649 ,  H01L29/872

摘要： An integrated circuit structure includes a semiconductor substrate; a first well region of a first conductivity type over the semiconductor substrate; a second well region of a second conductivity type opposite the first conductivity type encircling the first well region; and a metal-containing layer over and adjoining the first well region and extending over at least an inner portion of the second well region. The metal-containing layer and the first well region form a Schottky barrier. The integrated circuit structure further includes an isolation region encircling the metal-containing layer; and a third well region of the second conductivity type encircling at least a central portion of the first well region. The third well region has a higher impurity concentration than the second well region, and includes a top surface adjoining the metal-containing layer, and a bottom surface higher than bottom surfaces of the first and the second well regions.

摘要翻译： 集成电路结构包括半导体衬底; 半导体衬底上的第一导电类型的第一阱区; 与第一导电类型相反的第二导电类型的环绕第一阱区的第二阱区; 以及在所述第一阱区上并邻接所述第一阱区并且在所述第二阱区的至少内部部分上延伸的含金属层。 含金属层和第一阱区形成肖特基势垒。 所述集成电路结构还包括环绕所述含金属层的隔离区域; 以及第二导电类型的第三阱区域，其环绕至少第一阱区域的中心部分。 第三阱区域具有比第二阱区域更高的杂质浓度，并且包括邻近含金属层的顶表面和高于第一阱区域和第二阱区域的底表面的底表面。

公开(公告)号：US08324705B2

公开(公告)日：2012-12-04

申请号：US12127629

申请日：2008-05-27

申请人： Chien-Shao Tang ,  Dah-Chuen Ho ,  Yu-Chang Jong ,  Zhe-Yi Wang ,  Yuh-Hwa Chang ,  Yogendra Yadav

发明人： Chien-Shao Tang ,  Dah-Chuen Ho ,  Yu-Chang Jong ,  Zhe-Yi Wang ,  Yuh-Hwa Chang ,  Yogendra Yadav

IPC分类号： H01L29/872

CPC分类号： H01L27/0629 ,  H01L29/0619 ,  H01L29/0649 ,  H01L29/872

摘要： An integrated circuit structure includes a semiconductor substrate; a first well region of a first conductivity type over the semiconductor substrate; a second well region of a second conductivity type opposite the first conductivity type encircling the first well region; and a metal-containing layer over and adjoining the first well region and extending over at least an inner portion of the second well region. The metal-containing layer and the first well region form a Schottky barrier. The integrated circuit structure further includes an isolation region encircling the metal-containing layer; and a third well region of the second conductivity type encircling at least a central portion of the first well region. The third well region has a higher impurity concentration than the second well region, and includes a top surface adjoining the metal-containing layer, and a bottom surface higher than bottom surfaces of the first and the second well regions.

摘要翻译： 集成电路结构包括半导体衬底; 半导体衬底上的第一导电类型的第一阱区; 与第一导电类型相反的第二导电类型的环绕第一阱区的第二阱区; 以及在所述第一阱区上并邻接所述第一阱区并且在所述第二阱区的至少内部部分上延伸的含金属层。 含金属层和第一阱区形成肖特基势垒。 所述集成电路结构还包括环绕所述含金属层的隔离区域; 以及第二导电类型的第三阱区域，其环绕至少第一阱区域的中心部分。 第三阱区域具有比第二阱区域更高的杂质浓度，并且包括邻近含金属层的顶表面和高于第一阱区域和第二阱区域的底表面的底表面。

公开(公告)号：US07808069B2

公开(公告)日：2010-10-05

申请号：US12347478

申请日：2008-12-31

申请人： Dah-Chuen Ho ,  Chien-Shao Tang ,  Yu-Chang Jong ,  Zhe-Yi Wang

发明人： Dah-Chuen Ho ,  Chien-Shao Tang ,  Yu-Chang Jong ,  Zhe-Yi Wang

IPC分类号： H01L27/095

CPC分类号： H01L29/872 ,  H01L29/0619

摘要： A high-voltage Schottky diode including a deep P-well having a first width is formed on the semiconductor substrate. A doped P-well is disposed over the deep P-well and has a second width that is less than the width of the deep P-well. An M-type guard ring is formed around the upper surface of the second doped well, A Schottky metal is disposed on an upper surface of the second doped well and the N-type guard ring.

摘要翻译： 包括具有第一宽度的深P阱的高电压肖特基二极管形成在半导体衬底上。 掺杂的P阱设置在深P阱上，并且具有小于深P阱的宽度的第二宽度。 在第二掺杂阱的上表面周围形成M型保护环，肖特基金属设置在第二掺杂阱的上表面和N型保护环上。

公开(公告)号：US20090085112A1

公开(公告)日：2009-04-02

申请号：US11864278

申请日：2007-09-28

申请人： Dah-Chuen Ho ,  Chien-Shao Tang ,  Zhe-Yi Wang ,  Yu-Chang Jong

发明人： Dah-Chuen Ho ,  Chien-Shao Tang ,  Zhe-Yi Wang ,  Yu-Chang Jong

IPC分类号： H01L29/78

CPC分类号： H01L29/7835 ,  H01L29/0653 ,  H01L29/4933 ,  H01L29/66659

摘要： A lateral diffusion metal-oxide-semiconductor (LDMOS) structure comprises a gate, a source, a drain and a shallow trench isolation. The shallow trench isolation is formed between the drain and the gate to withstand high voltages, applied to the drain, and is associated with the semiconductor substrate to form a recess. As such, the surface of the shallow trench isolation is lower than the surface of the semiconductor substrate. Optionally, the surface of the shallow trench isolation is lower than the surface of the semiconductor substrate by 300-1500 angstroms.

摘要翻译： 横向扩散金属氧化物半导体（LDMOS）结构包括栅极，源极，漏极和浅沟槽隔离。 浅沟槽隔离形成在漏极和栅极之间以承受施加到漏极上的高电压，并且与半导体衬底相关联以形成凹部。 因此，浅沟槽隔离的表面低于半导体衬底的表面。 可选地，浅沟槽隔离的表面比半导体衬底的表面低300-1500埃。

公开(公告)号：US20080073745A1

公开(公告)日：2008-03-27

申请号：US11526419

申请日：2006-09-25

申请人： Chien-Shao Tang ,  Tsung-Yi Huang ,  David Ho ,  Zhe-Yi Wang ,  Yu-Chang Jong

发明人： Chien-Shao Tang ,  Tsung-Yi Huang ,  David Ho ,  Zhe-Yi Wang ,  Yu-Chang Jong

IPC分类号： H01L29/00

CPC分类号： H01L29/0847 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823456 ,  H01L21/823481 ,  H01L21/823493 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7833 ,  H01L29/7835

摘要： A high-voltage semiconductor structure includes a high-voltage well region overlying a substrate, an isolation region extending from a top surface of the high-voltage well region into the high-voltage well region, a low-voltage well region having at least a portion underlying and adjoining the isolation region wherein the low-voltage well region is inside of and of a same conductivity type as the high-voltage well region, a gate dielectric on the high-voltage well region, a gate electrode on the gate dielectric, and a source/drain region of the same conductivity type as the high-voltage well region, wherein the source/drain region is spaced apart from a channel region by the isolation region.

摘要翻译： 高电压半导体结构包括覆盖基板的高电压阱区域，从高压阱区域的顶表面延伸到高压阱区域的隔离区域，具有至少一个 隔离区域的底部和邻接部分，其中低电压阱区域在与高压阱区域相同的导电类型内，高电压阱区域上的栅极电介质，栅极电介质上的栅电极， 以及与高电压阱区相同导电类型的源/漏区，其中源极/漏极区通过隔离区与沟道区间隔开。