公开(公告)号：US07608889B2

公开(公告)日：2009-10-27

申请号：US11864278

申请日：2007-09-28

申请人： Dah-Chuen Ho ,  Chien-Shao Tang ,  Zhe-Yi Wang ,  Yu-Chang Jong

发明人： Dah-Chuen Ho ,  Chien-Shao Tang ,  Zhe-Yi Wang ,  Yu-Chang Jong

IPC分类号： H01L29/78

CPC分类号： H01L29/7835 ,  H01L29/0653 ,  H01L29/4933 ,  H01L29/66659

摘要： A lateral diffusion metal-oxide-semiconductor (LDMOS) structure comprises a gate, a source, a drain and a shallow trench isolation. The shallow trench isolation is formed between the drain and the gate to withstand high voltages, applied to the drain, and is associated with the semiconductor substrate to form a recess. As such, the surface of the shallow trench isolation is lower than the surface of the semiconductor substrate. Optionally, the surface of the shallow trench isolation is lower than the surface of the semiconductor substrate by 300-1500 angstroms.

摘要翻译： 横向扩散金属氧化物半导体（LDMOS）结构包括栅极，源极，漏极和浅沟槽隔离。 浅沟槽隔离形成在漏极和栅极之间以承受施加到漏极上的高电压，并且与半导体衬底相关联以形成凹部。 因此，浅沟槽隔离的表面低于半导体衬底的表面。 可选地，浅沟槽隔离的表面比半导体衬底的表面低300-1500埃。

公开(公告)号：US20090294865A1

公开(公告)日：2009-12-03

申请号：US12127629

申请日：2008-05-27

申请人： Chien-Shao Tang ,  Dah-Chuen Ho ,  Yu-Chang Jong ,  Zhe-Yi Wang ,  Yuh-Hwa Chang ,  Yogendra Yadav

发明人： Chien-Shao Tang ,  Dah-Chuen Ho ,  Yu-Chang Jong ,  Zhe-Yi Wang ,  Yuh-Hwa Chang ,  Yogendra Yadav

IPC分类号： H01L27/06

CPC分类号： H01L27/0629 ,  H01L29/0619 ,  H01L29/0649 ,  H01L29/872

摘要： An integrated circuit structure includes a semiconductor substrate; a first well region of a first conductivity type over the semiconductor substrate; a second well region of a second conductivity type opposite the first conductivity type encircling the first well region; and a metal-containing layer over and adjoining the first well region and extending over at least an inner portion of the second well region. The metal-containing layer and the first well region form a Schottky barrier. The integrated circuit structure further includes an isolation region encircling the metal-containing layer; and a third well region of the second conductivity type encircling at least a central portion of the first well region. The third well region has a higher impurity concentration than the second well region, and includes a top surface adjoining the metal-containing layer, and a bottom surface higher than bottom surfaces of the first and the second well regions.

摘要翻译： 集成电路结构包括半导体衬底; 半导体衬底上的第一导电类型的第一阱区; 与第一导电类型相反的第二导电类型的环绕第一阱区的第二阱区; 以及在所述第一阱区上并邻接所述第一阱区并且在所述第二阱区的至少内部部分上延伸的含金属层。 含金属层和第一阱区形成肖特基势垒。 所述集成电路结构还包括环绕所述含金属层的隔离区域; 以及第二导电类型的第三阱区域，其环绕至少第一阱区域的中心部分。 第三阱区域具有比第二阱区域更高的杂质浓度，并且包括邻近含金属层的顶表面和高于第一阱区域和第二阱区域的底表面的底表面。

公开(公告)号：US08324705B2

公开(公告)日：2012-12-04

申请号：US12127629

申请日：2008-05-27

申请人： Chien-Shao Tang ,  Dah-Chuen Ho ,  Yu-Chang Jong ,  Zhe-Yi Wang ,  Yuh-Hwa Chang ,  Yogendra Yadav

发明人： Chien-Shao Tang ,  Dah-Chuen Ho ,  Yu-Chang Jong ,  Zhe-Yi Wang ,  Yuh-Hwa Chang ,  Yogendra Yadav

IPC分类号： H01L29/872

CPC分类号： H01L27/0629 ,  H01L29/0619 ,  H01L29/0649 ,  H01L29/872

摘要： An integrated circuit structure includes a semiconductor substrate; a first well region of a first conductivity type over the semiconductor substrate; a second well region of a second conductivity type opposite the first conductivity type encircling the first well region; and a metal-containing layer over and adjoining the first well region and extending over at least an inner portion of the second well region. The metal-containing layer and the first well region form a Schottky barrier. The integrated circuit structure further includes an isolation region encircling the metal-containing layer; and a third well region of the second conductivity type encircling at least a central portion of the first well region. The third well region has a higher impurity concentration than the second well region, and includes a top surface adjoining the metal-containing layer, and a bottom surface higher than bottom surfaces of the first and the second well regions.

摘要翻译： 集成电路结构包括半导体衬底; 半导体衬底上的第一导电类型的第一阱区; 与第一导电类型相反的第二导电类型的环绕第一阱区的第二阱区; 以及在所述第一阱区上并邻接所述第一阱区并且在所述第二阱区的至少内部部分上延伸的含金属层。 含金属层和第一阱区形成肖特基势垒。 所述集成电路结构还包括环绕所述含金属层的隔离区域; 以及第二导电类型的第三阱区域，其环绕至少第一阱区域的中心部分。 第三阱区域具有比第二阱区域更高的杂质浓度，并且包括邻近含金属层的顶表面和高于第一阱区域和第二阱区域的底表面的底表面。

公开(公告)号：US07808069B2

公开(公告)日：2010-10-05

申请号：US12347478

申请日：2008-12-31

申请人： Dah-Chuen Ho ,  Chien-Shao Tang ,  Yu-Chang Jong ,  Zhe-Yi Wang

发明人： Dah-Chuen Ho ,  Chien-Shao Tang ,  Yu-Chang Jong ,  Zhe-Yi Wang

IPC分类号： H01L27/095

CPC分类号： H01L29/872 ,  H01L29/0619

摘要： A high-voltage Schottky diode including a deep P-well having a first width is formed on the semiconductor substrate. A doped P-well is disposed over the deep P-well and has a second width that is less than the width of the deep P-well. An M-type guard ring is formed around the upper surface of the second doped well, A Schottky metal is disposed on an upper surface of the second doped well and the N-type guard ring.

摘要翻译： 包括具有第一宽度的深P阱的高电压肖特基二极管形成在半导体衬底上。 掺杂的P阱设置在深P阱上，并且具有小于深P阱的宽度的第二宽度。 在第二掺杂阱的上表面周围形成M型保护环，肖特基金属设置在第二掺杂阱的上表面和N型保护环上。

公开(公告)号：US20090085112A1

公开(公告)日：2009-04-02

申请号：US11864278

申请日：2007-09-28

申请人： Dah-Chuen Ho ,  Chien-Shao Tang ,  Zhe-Yi Wang ,  Yu-Chang Jong

发明人： Dah-Chuen Ho ,  Chien-Shao Tang ,  Zhe-Yi Wang ,  Yu-Chang Jong

IPC分类号： H01L29/78

CPC分类号： H01L29/7835 ,  H01L29/0653 ,  H01L29/4933 ,  H01L29/66659

摘要： A lateral diffusion metal-oxide-semiconductor (LDMOS) structure comprises a gate, a source, a drain and a shallow trench isolation. The shallow trench isolation is formed between the drain and the gate to withstand high voltages, applied to the drain, and is associated with the semiconductor substrate to form a recess. As such, the surface of the shallow trench isolation is lower than the surface of the semiconductor substrate. Optionally, the surface of the shallow trench isolation is lower than the surface of the semiconductor substrate by 300-1500 angstroms.

摘要翻译： 横向扩散金属氧化物半导体（LDMOS）结构包括栅极，源极，漏极和浅沟槽隔离。 浅沟槽隔离形成在漏极和栅极之间以承受施加到漏极上的高电压，并且与半导体衬底相关联以形成凹部。 因此，浅沟槽隔离的表面低于半导体衬底的表面。 可选地，浅沟槽隔离的表面比半导体衬底的表面低300-1500埃。

公开(公告)号：US20080073745A1

公开(公告)日：2008-03-27

申请号：US11526419

申请日：2006-09-25

申请人： Chien-Shao Tang ,  Tsung-Yi Huang ,  David Ho ,  Zhe-Yi Wang ,  Yu-Chang Jong

发明人： Chien-Shao Tang ,  Tsung-Yi Huang ,  David Ho ,  Zhe-Yi Wang ,  Yu-Chang Jong

IPC分类号： H01L29/00

CPC分类号： H01L29/0847 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823456 ,  H01L21/823481 ,  H01L21/823493 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7833 ,  H01L29/7835

摘要： A high-voltage semiconductor structure includes a high-voltage well region overlying a substrate, an isolation region extending from a top surface of the high-voltage well region into the high-voltage well region, a low-voltage well region having at least a portion underlying and adjoining the isolation region wherein the low-voltage well region is inside of and of a same conductivity type as the high-voltage well region, a gate dielectric on the high-voltage well region, a gate electrode on the gate dielectric, and a source/drain region of the same conductivity type as the high-voltage well region, wherein the source/drain region is spaced apart from a channel region by the isolation region.

摘要翻译： 高电压半导体结构包括覆盖基板的高电压阱区域，从高压阱区域的顶表面延伸到高压阱区域的隔离区域，具有至少一个 隔离区域的底部和邻接部分，其中低电压阱区域在与高压阱区域相同的导电类型内，高电压阱区域上的栅极电介质，栅极电介质上的栅电极， 以及与高电压阱区相同导电类型的源/漏区，其中源极/漏极区通过隔离区与沟道区间隔开。

公开(公告)号：US07081662B1

公开(公告)日：2006-07-25

申请号：US11199833

申请日：2005-08-09

申请人： Jian-Hsing Lee ,  Yu-Chang Jong

发明人： Jian-Hsing Lee ,  Yu-Chang Jong

IPC分类号： H01L29/00 ,  H01L29/73

CPC分类号： H01L27/0259

摘要： An electrostatic discharge (ESD) protection structure and a method for forming the same are provided. The structure includes a substrate having a buried layer, and a first and a second high-voltage well region on the buried layer. The first and second high-voltage well regions have opposite conductivity types and physically contact each other. The structure further includes a field region extending from the first high-voltage well region into the second high-voltage well region, a first doped region in the first high-voltage well region and physically contacting the field region, and a second doped region in the second high-voltage well region and physically contacting the field region. The first and second doped regions and the first high-voltage well region form a bipolar transistor that can protect an integrated circuit from ESD.

摘要翻译： 提供一种静电放电（ESD）保护结构及其形成方法。 该结构包括具有掩埋层的衬底以及掩埋层上的第一和第二高压阱区。 第一和第二高电压阱区具有相反的导电类型并且物理上彼此接触。 该结构还包括从第一高电压阱区域延伸到第二高电压阱区域的场区域，第一高压阱区域中的第一掺杂区域和与场区域物理接触的第二掺杂区域， 第二高压井区域并物理接触场区域。 第一和第二掺杂区域和第一高电压阱区域形成可以保护集成电路免受ESD的双极晶体管。

公开(公告)号：US08344416B2

公开(公告)日：2013-01-01

申请号：US12777672

申请日：2010-05-11

申请人： Ming-Song Sheu ,  Jian-Hsing Lee ,  Yu-Chang Jong ,  Chun-Chien Tsai

发明人： Ming-Song Sheu ,  Jian-Hsing Lee ,  Yu-Chang Jong ,  Chun-Chien Tsai

IPC分类号： H01L29/02

CPC分类号： H01L27/0251 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/66681 ,  H01L29/7817 ,  H01L29/7835

摘要： An integrated circuit includes at least one transistor over a substrate. A first guard ring is disposed around the at least one transistor. The first guard ring has a first type dopant. A second guard ring is disposed around the first guard ring. The second guard ring has a second type dopant. A first doped region is disposed adjacent to the first guard ring. The first doped region has the second type dopant. A second doped region is disposed adjacent to the second guard ring. The second doped region has the first type dopant. The first guard ring, the second guard ring, the first doped region, and the second doped region are capable of being operable as a first silicon controlled rectifier (SCR) to substantially release an electrostatic discharge (ESD).

摘要翻译： 集成电路在衬底上包括至少一个晶体管。 第一保护环布置在至少一个晶体管周围。 第一保护环具有第一类型掺杂剂。 第二保护环设置在第一保护环周围。 第二保护环具有第二类型掺杂剂。 第一掺杂区域邻近第一保护环设置。 第一掺杂区具有第二类掺杂剂。 第二掺杂区域邻近第二保护环设置。 第二掺杂区具有第一类掺杂剂。 第一保护环，第二保护环，第一掺杂区和第二掺杂区能够用作第一可控硅整流器（SCR），以基本上释放静电放电（ESD）。

公开(公告)号：US07521741B2

公开(公告)日：2009-04-21

申请号：US11593424

申请日：2006-11-06

申请人： Yu-Chang Jong ,  Ruey-Hsin Liu ,  Yueh-Chiou Lin ,  Shun-Liang Hsu ,  Chi-Hsuen Chang ,  Te-Yin Hsia

发明人： Yu-Chang Jong ,  Ruey-Hsin Liu ,  Yueh-Chiou Lin ,  Shun-Liang Hsu ,  Chi-Hsuen Chang ,  Te-Yin Hsia

IPC分类号： H01L29/76

CPC分类号： H01L29/7834 ,  H01L29/0653 ,  H01L29/0692

摘要： A high-voltage MOS device includes a first high-voltage well (HVW) region overlying a substrate, a second HVW region overlying the substrate, a third HVW region of an opposite conductivity type as that of the first and the second HVW regions overlying the substrate, wherein the HVPW region has at least a portion between the first HVNW region and the second HVNW region, an insulation region in the first HVNW region, the second HVNW region, and the HVPW region, a gate dielectric over and extending from the first HVNW region to the second HVNW region, a gate electrode on the gate dielectric, and a shielding pattern electrically insulated from the gate electrode over the insulation region. Preferably, the gate electrode and the shielding pattern have a spacing of less than about 0.4 μm. The shielding pattern is preferably connected to a voltage lower than a stress voltage applied on the gate electrode.

摘要翻译： 高压MOS器件包括覆盖衬底的第一高电压阱（HVW）区域，覆盖衬底的第二HVW区域，与覆盖衬底的第一和第二HVW区域相反的导电类型的第三HVW区域 基板，其中所述HVPW区域具有在所述第一HVNW区域和所述第二HVNW区域之间的至少一部分，所述第一HVNW区域中的绝缘区域，所述第二HVNW区域和所述HVPW区域，在所述第一HVNW区域和所述第二HVNW区域之间延伸的栅极电介质 HVNW区域到第二HVNW区域，栅极电介质上的栅极电极以及在绝缘区域上与栅电极电绝缘的屏蔽图案。 优选地，栅电极和屏蔽图案具有小于约0.4μm的间隔。 屏蔽图案优选地连接到低于施加在栅电极上的应力电压的电压。

公开(公告)号：US07384802B2

公开(公告)日：2008-06-10

申请号：US11438603

申请日：2006-05-22

申请人： Jian-Hsing Lee ,  Yu-Chang Jong

发明人： Jian-Hsing Lee ,  Yu-Chang Jong

IPC分类号： H01L21/00

CPC分类号： H01L27/0259

摘要： An electrostatic discharge (ESD) protection structure and a method for forming the same are provided. The structure includes a substrate having a buried layer, and a first and a second high-voltage well region on the buried layer. The first and second high-voltage well regions have opposite conductivity types and physically contact each other. The structure further includes a field region extending from the first high-voltage well region into the second high-voltage well region, a first doped region in the first high-voltage well region and physically contacting the field region, and a second doped region in the second high-voltage well region and physically contacting the field region. The first and second doped regions and the first high-voltage well region form a bipolar transistor that can protect an integrated circuit from ESD.

摘要翻译： 提供一种静电放电（ESD）保护结构及其形成方法。 该结构包括具有掩埋层的衬底以及掩埋层上的第一和第二高压阱区。 第一和第二高电压阱区具有相反的导电类型并且物理上彼此接触。 该结构还包括从第一高电压阱区域延伸到第二高电压阱区域的场区域，第一高压阱区域中的第一掺杂区域和与场区域物理接触的第二掺杂区域， 第二高压井区域并物理接触场区域。 第一和第二掺杂区域和第一高电压阱区域形成可以保护集成电路免受ESD的双极晶体管。