公开(公告)号：US20090024810A1

公开(公告)日：2009-01-22

申请号：US12219051

申请日：2008-07-15

申请人： Daisuke Ito ,  Shinji Fujiwara ,  Kazuo Otsuga ,  Shinya Kajiyama

发明人： Daisuke Ito ,  Shinji Fujiwara ,  Kazuo Otsuga ,  Shinya Kajiyama

IPC分类号： G06F12/00

CPC分类号： G06F12/0246

摘要： In a storage device, a method is provided for preventing the risk of data loss and a significant decrease of writing speed due to area shrinkage when erased erase blocks have become fewer. A process of allocating a new page includes determining whether the length of a deallocated pages list is longer than n pages. If the list length is longer, one page is allocated from the deallocated pages list. If the list length is shorter, a capacity shortage error returns. Deleting a file using an erased pages list includes determining whether a page to be processed is emptied by deleting the file. If not so, the file is deleted from the page. If so, the contents of the last page-a in occupied pages are copied to the page, the page-a is written with data for erasure, and any erase block included in the page-a is made erasable.

摘要翻译： 在存储装置中，提供了一种防止数据丢失的风险的方法，并且当擦除擦除块变得更少时，由于面积缩小而显着降低写入速度。 分配新页面的过程包括确定取消分配页面列表的长度是否长于n页。 如果列表长度较长，则从取消分配的页面列表中分配一个页面。 如果列表长度较短，则容量短缺错误返回。 使用删除的页面列表删除文件包括确定要处理的页面是否通过删除文件被清空。 如果不是这样，该文件将从页面中删除。 如果是这样，被占用页面中的最后一页的内容被复制到页面，页面a被写入用于擦除的数据，并且包含在页面a中的任何擦除块被擦除。

公开(公告)号：US07954023B2

公开(公告)日：2011-05-31

申请号：US12342015

申请日：2008-12-22

申请人： Kazuo Otsuga ,  Kenichi Osada ,  Yusuke Kanno

发明人： Kazuo Otsuga ,  Kenichi Osada ,  Yusuke Kanno

IPC分类号： G01R31/28

CPC分类号： H03K19/0016

摘要： A scan chain configuration and a control method for the same are provided, which are optimized for the leakage current reduction technique by a vector input in SoC in which many functional blocks are mounted. The semiconductor integrated circuit includes: plural power domains (Area1-AreaN) which have plural functional blocks; power switches (PSW1-PSWN) which can supply a power source for operation to the power domains; a scan chain provided for every power domain, and a memory unit (VEC) which supplies, to a scan chain, a vector to enable shifting to a low-leakage state. By re-coupling the scan chain only to a non-operating functional block, it is possible to perform shifting to a low-leakage state for a short time.

摘要翻译： 提供了一种扫描链配置及其控制方法，其通过SoC中的矢量输入针对泄漏电流降低技术进行了优化，其中安装了许多功能块。 半导体集成电路包括：具有多个功能块的多个电力域（Area1-AreaN） 电源开关（PSW1-PSWN），可以向电源区域提供运行的电源; 为每个功率域提供的扫描链，以及向扫描链提供矢量以使其能够转换到低泄漏状态的存储器单元（VEC）。 通过将扫描链重新耦合到非操作功能块，可以在短时间内进行低泄漏状态的切换。

公开(公告)号：US07323741B2

公开(公告)日：2008-01-29

申请号：US10998630

申请日：2004-11-30

申请人： Kazuo Otsuga ,  Hideaki Kurata ,  Yoshitaka Sasago

发明人： Kazuo Otsuga ,  Hideaki Kurata ,  Yoshitaka Sasago

IPC分类号： H01L29/788 ,  H01L29/76 ,  H01L29/94 ,  H01L31/00

CPC分类号： H01L29/7885 ,  G11C11/5621 ,  G11C16/0433 ,  G11C16/0491 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42328

摘要： A low cost semiconductor nonvolatile memory device capable of high speed programming, using an inversion layer as the wiring, and a manufacturing method for that device. The semiconductor memory device includes an auxiliary electrode at a position between and in parallel with the source and drain regions and with no position overlap versus the source region and the drain region formed mutually in parallel; wherein the auxiliary electrode for hot electron source injection is utilized as the auxiliary electrode for programming (writing); and an inversion layer formed below the auxiliary electrode is utilized as the source region or as the drain region during the read operation.

摘要翻译： 能够使用反转层作为布线的能够进行高速编程的低成本半导体非易失性存储器件以及该器件的制造方法。 半导体存储器件包括在源极和漏极区域之间并与之平行的位置处的辅助电极，并且与相互平行形成的源极区域和漏极区域没有位置重叠; 其中用于热电子源注入的辅助电极用作编程（写入）的辅助电极; 并且在读取操作期间，在辅助电极下形成的反型层用作源极区域或漏极区域。

公开(公告)号：US20060039195A1

公开(公告)日：2006-02-23

申请号：US11197485

申请日：2005-08-05

申请人： Hideaki Kurata ,  Kazuo Otsuga ,  Yoshitaka Sasago ,  Takashi Kobayashi ,  Tsuyoshi Arigane

发明人： Hideaki Kurata ,  Kazuo Otsuga ,  Yoshitaka Sasago ,  Takashi Kobayashi ,  Tsuyoshi Arigane

IPC分类号： G11C16/04

CPC分类号： H01L27/11521 ,  G11C16/0425 ,  G11C16/0433 ,  G11C16/12 ,  G11C16/3459 ,  H01L27/115 ,  H01L27/11524

摘要： Suppressing a leakage current is required in a flash memory because the channel length is made shorter with a reduction in the memory cell size. In an AND type memory array having an assist electrode, although the memory cell area has been reduced by the field isolation using a MOS transistor, leakage current in the channel direction becomes greater with a reduction in the memory cell size, resulting in problems arising like deterioration of programming characteristics, an increase in the current consumption, and reading failure. To achieve the objective, in the present invention, electrical isolation is performed by controlling at least one assist electrode of the assist electrodes wired in parallel to be a negative voltage during program and read operations and by making the semiconductor substrate surface in the vicinity of the aforementioned assist electrode non-conductive.

摘要翻译： 在闪速存储器中需要抑制泄漏电流，因为随着存储器单元尺寸的减小，通道长度变短。 在具有辅助电极的AND型存储器阵列中，虽然通过使用MOS晶体管的场隔离来减小存储单元面积，但是由于存储单元尺寸的减小，沟道方向的泄漏电流变大，导致出现像 编程特性恶化，电流消耗增加，读取失败。 为了实现该目的，在本发明中，通过在编程和读取操作期间将辅助电极并联布置的至少一个辅助电极作为负电压进行电隔离，并且通过使半导体衬底表面在 上述辅助电极不导电。

公开(公告)号：US20050127429A1

公开(公告)日：2005-06-16

申请号：US10998630

申请日：2004-11-30

申请人： Kazuo Otsuga ,  Hideaki Kurata ,  Yoshitaka Sasago

发明人： Kazuo Otsuga ,  Hideaki Kurata ,  Yoshitaka Sasago

IPC分类号： G11C16/02 ,  G11C11/56 ,  G11C16/04 ,  G11C16/06 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L29/7885 ,  G11C11/5621 ,  G11C16/0433 ,  G11C16/0491 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42328

摘要： A low cost semiconductor nonvolatile memory device capable of high speed programming, using an inversion layer as the wiring, and a manufacturing method for that device. The semiconductor memory device includes an auxiliary electrode at a position between and in parallel with the source and drain regions and with no position overlap versus the source region and the drain region formed mutually in parallel; wherein the auxiliary electrode for hot electron source injection is utilized as the auxiliary electrode for programming (writing); and an inversion layer formed below the auxiliary electrode is utilized as the source region or as the drain region during the read operation.

摘要翻译： 能够使用反转层作为布线的能够进行高速编程的低成本半导体非易失性存储器件以及该器件的制造方法。 半导体存储器件包括在源极和漏极区域之间并与之平行的位置处的辅助电极，并且与相互平行形成的源极区域和漏极区域没有位置重叠; 其中用于热电子源注入的辅助电极用作编程（写入）的辅助电极; 并且在读取操作期间，在辅助电极下形成的反型层用作源极区域或漏极区域。

公开(公告)号：US08030956B2

公开(公告)日：2011-10-04

申请号：US12878564

申请日：2010-09-09

申请人： Kazuo Otsuga ,  Tetsuya Yamada ,  Kenichi Osada ,  Yusuke Kanno

发明人： Kazuo Otsuga ,  Tetsuya Yamada ,  Kenichi Osada ,  Yusuke Kanno

IPC分类号： G01R31/3187 ,  G01R31/28

CPC分类号： G01R19/0092 ,  Y10T307/406

摘要： A semiconductor integrated circuit that includes a circuit block having a predetermined function, a power switch capable of supplying an operating power to the circuit block, and a current measuring circuit for obtaining a current flowing to the circuit block based on a voltage between terminals of the power switch in a state in which the power switch is turned on and an on-resistance of the power switch. Thus, it is possible to measure a current of the circuit block in a state in which a chip is normally operated.

摘要翻译： 一种半导体集成电路，包括具有预定功能的电路块，能够向电路块提供工作电力的电源开关，以及电流测量电路，用于根据电流块的端子之间的电压来获得流向电路块的电流 电源开关处于电源开关接通的状态和电源开关的导通电阻。 因此，可以在芯片正常工作的状态下测量电路块的电流。

公开(公告)号：US07812628B2

公开(公告)日：2010-10-12

申请号：US11956122

申请日：2007-12-13

申请人： Kazuo Otsuga ,  Tetsuya Yamada ,  Kenichi Osada ,  Yusuke Kanno

发明人： Kazuo Otsuga ,  Tetsuya Yamada ,  Kenichi Osada ,  Yusuke Kanno

IPC分类号： G01R31/26

CPC分类号： G01R19/0092 ,  Y10T307/406

摘要： A semiconductor integrated circuit is constituted to include a circuit block having a predetermined function, a power switch capable of supplying an operating power to the circuit block, and a current measuring circuit for obtaining a current flowing to the circuit block based on a voltage between terminals of the power switch in a state in which the power switch is turned on and an on-resistance of the power switch. The current flowing to the circuit block is obtained based on the voltage between terminals of the power switch in the state in which the power switch is turned on and the on-resistance of the power switch. Thus, it is possible to measure a current of the circuit block in a state in which a chip is normally operated.

摘要翻译： 半导体集成电路被构成为包括具有预定功能的电路块，能够向电路块提供工作电力的电源开关，以及电流测量电路，用于根据端子之间的电压获得流向电路块的电流 电源开关处于电源开关接通的状态和电源开关的导通电阻。 基于电源开关接通状态和电源开关的导通电阻之间的电源开关电压之间的电流可以获得流向电路块的电流。 因此，可以在芯片正常工作的状态下测量电路块的电流。

公开(公告)号：US08248099B2

公开(公告)日：2012-08-21

申请号：US12787090

申请日：2010-05-25

申请人： Kazuo Otsuga ,  Yusuke Kanno

发明人： Kazuo Otsuga ,  Yusuke Kanno

IPC分类号： G01R31/28

CPC分类号： G01R31/31721

摘要： In a semiconductor integrated circuit wherein low-threshold-voltage and high-threshold-voltage transistors are disposed mixedly, the operating speed of each transistor can be properly controlled in speed control execution through regulation of a power supply voltage VDD. The semiconductor integrated circuit comprises an internal circuit and measuring circuits. The internal circuit comprises a low-threshold-voltage MOS transistor and a high-threshold-voltage MOS transistor, and the degree of threshold voltage variation of the low-threshold-voltage MOS transistor is larger than the degree of threshold voltage variation of the high-threshold-voltage MOS transistor. The measuring circuit detects which one of fast, typical, and slow states is taken by both the low-threshold-voltage MOS transistor and the high-threshold-voltage MOS transistor. When the result data detected indicates the fast state, the power supply voltage VDD is set to a lower power supply voltage level “VDD−ΔVDD” corresponding to a small variation gradient “β[V/σ]”. When the result data detected indicates the typical state, the power supply voltage VDD is set to an intermediate power supply voltage level “VDD±0”. When the result data detected indicates the slow state, the power supply voltage VDD is set to a higher power supply voltage level “VDD+ΔVDD” corresponding to a large variation gradient “α[V/σ]”.

摘要翻译： 在其中低阈值电压和高阈值电压晶体管被混合地布置的半导体集成电路中，通过调节电源电压VDD可以在速度控制执行中适当地控制每个晶体管的工作速度。 半导体集成电路包括内部电路和测量电路。 内部电路包括低阈值电压MOS晶体管和高阈值电压MOS晶体管，并且低阈值电压MOS晶体管的阈值电压变化程度大于高阈值电压MOS晶体管的阈值电压变化的程度 阈值电压MOS晶体管。 测量电路检测低阈值电压MOS晶体管和高阈值电压MOS晶体管中的哪一个快速，典型和慢速状态。 当检测到的结果数据指示快速状态时，电源电压VDD被设置为对应于小变化梯度“＆bgr; [V /＆sgr]]的较低电源电压电平”VDD-＆Dgr; VDD“。 当检测到的结果数据表示典型状态时，将电源电压VDD设定为中间电源电压电平“VDD±0”。 当检测到的结果数据表示慢速状态时，将电源电压VDD设定为与较大变化梯度“α[V /＆sgr”]对应的较高电源电压电平“VDD +＆Dgr; VDD”。

公开(公告)号：US20070109870A1

公开(公告)日：2007-05-17

申请号：US11652023

申请日：2007-01-11

申请人： Hideaki Kurata ,  Kazuo Otsuga ,  Yoshitaka Sasago ,  Takashi Kobayashi ,  Tsuyoshi Arigane

发明人： Hideaki Kurata ,  Kazuo Otsuga ,  Yoshitaka Sasago ,  Takashi Kobayashi ,  Tsuyoshi Arigane

IPC分类号： G11C16/04

CPC分类号： H01L27/11521 ,  G11C16/0425 ,  G11C16/0433 ,  G11C16/12 ,  G11C16/3459 ,  H01L27/115 ,  H01L27/11524

摘要： Suppressing a leakage current is required in a flash memory because the channel length is made shorter with a reduction in the memory cell size. In an AND type memory array having an assist electrode, although the memory cell area has been reduced by the field isolation using a MOS transistor, leakage current in the channel direction becomes greater with a reduction in the memory cell size, resulting in problems arising like deterioration of programming characteristics, an increase in the current consumption, and reading failure. To achieve the objective, in the present invention, electrical isolation is performed by controlling at least one assist electrode of the assist electrodes wired in parallel to be a negative voltage during program and read operations and by making the semiconductor substrate surface in the vicinity of the aforementioned assist electrode non-conductive.

摘要翻译： 在闪速存储器中需要抑制泄漏电流，因为随着存储器单元尺寸的减小，通道长度变短。 在具有辅助电极的AND型存储器阵列中，虽然通过使用MOS晶体管的场隔离来减小存储单元面积，但是由于存储单元尺寸的减小，沟道方向的泄漏电流变大，导致出现像 编程特性恶化，电流消耗增加，读取失败。 为了实现该目的，在本发明中，通过在编程和读取操作期间将辅助电极并联布置的至少一个辅助电极作为负电压进行电隔离，并且通过使半导体衬底表面在 上述辅助电极不导电。

公开(公告)号：US07184318B2

公开(公告)日：2007-02-27

申请号：US11197485

申请日：2005-08-05

申请人： Hideaki Kurata ,  Kazuo Otsuga ,  Yoshitaka Sasago ,  Takashi Kobayashi ,  Tsuyoshi Arigane

发明人： Hideaki Kurata ,  Kazuo Otsuga ,  Yoshitaka Sasago ,  Takashi Kobayashi ,  Tsuyoshi Arigane

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： H01L27/11521 ,  G11C16/0425 ,  G11C16/0433 ,  G11C16/12 ,  G11C16/3459 ,  H01L27/115 ,  H01L27/11524

摘要： Suppressing a leakage current is required in a flash memory because the channel length is made shorter with a reduction in the memory cell size. In an AND type memory array having an assist electrode, although the memory cell area has been reduced by the field isolation using a MOS transistor, leakage current in the channel direction becomes greater with a reduction in the memory cell size, resulting in problems arising like deterioration of programming characteristics, an increase in the current consumption, and reading failure. To achieve the objective, in the present invention, electrical isolation is performed by controlling at least one assist electrode of the assist electrodes wired in parallel to be a negative voltage during program and read operations and by making the semiconductor substrate surface in the vicinity of the aforementioned assist electrode non-conductive.