公开(公告)号：US06223313B1

公开(公告)日：2001-04-24

申请号：US08985790

申请日：1997-12-05

申请人： Dana How ,  Adi Srinivasan ,  Robert Osann ,  Shridhar Mukund

发明人： Dana How ,  Adi Srinivasan ,  Robert Osann ,  Shridhar Mukund

IPC分类号： G01R3128

CPC分类号： G01R31/318516

摘要： A system for testing an integrated circuit, and particularly a gate array, is disclosed which includes, prior to coupling the array to form a user-designed circuit, predesigned logic that enables testing of the user-designed circuit. The predesigned logic allows logic blocks in the array to operate in “freeze” mode or to operate in normal mode, where normal mode is defined by the user-designed circuit. Much of the same circuitry in the logic blocks is, in fact, used in both modes of operation, thus minimizing circuitry added due to test. When the logic blocks are selected to be frozen, the logic blocks behave as a series of daisy-chained master-slave flip-flops. Stimulus data is shifted into the array and captured data is shifted out of the array through the daisy-chained flip-flops. Nonetheless, when data is shifted into and out of the daisy-chained flip-flops, the master latch and the slave latch of each flip-flop can be set to receive independent values and the data captured by each of the master and slave latches can be independently shifted out and analyzed. Although when frozen, the logic blocks behave as daisy-chained flip-flops, use of the logic blocks for testing purposes does not depend upon placement of sequential elements in the user-designed circuit in the logic blocks. In other words, in normal mode, a logic block can implement combinational, sequential, or other functions and still later be used to drive out stimulus values or capture results. Moreover, each logic block is further equipped for addressable mode control, allowing selected logic blocks to be exercised in isolation once stimulus data is shifted in, simplifying test generation and improving fault coverage. Using a logic block in accordance with the invention results in a high level of fault coverage, while placing few limitations on the user's circuit design.

摘要翻译： 公开了用于测试集成电路，特别是门阵列的系统，其包括在耦合阵列以形成用户设计的电路之前，预先设计的逻辑，其能够测试用户设计的电路。 预先设计的逻辑允许阵列中的逻辑块以“冻结”模式运行或在正常模式下运行，其中正常模式由用户设计的电路定义。 事实上，逻辑块中的大部分相同的电路用于两种工作模式，从而最小化由于测试而添加的电路。 当逻辑块被选择为冻结时，逻辑块表现为一系列菊花链主主机触发器。 激励数据移入阵列，捕获的数据通过菊花链式触发器从阵列中移出。 然而，当数据被移入和移出菊花链触发器时，每个触发器的主锁存器和从锁存器可被设置为接收独立的值，并且由每个主锁存器和从锁存器捕获的数据可以 独立移出并分析。 尽管在冻结时，逻辑块表现为菊花链式触发器，但用于测试目的的逻辑块的使用并不取决于逻辑块中用户设计的电路中顺序元件的位置。 换句话说，在正常模式下，逻辑块可以实现组合，顺序或其他功能，并且稍后可用于驱出刺激值或捕获结果。 此外，每个逻辑块进一步配置为可寻址模式控制，允许一旦激励数据被移位，孤立地选择逻辑块，简化测试生成并提高故障覆盖。 使用根据本发明的逻辑块导致高水平的故障覆盖，同时对用户的电路设计几乎没有限制。

公开(公告)号：US06611932B2

公开(公告)日：2003-08-26

申请号：US10056686

申请日：2002-01-24

申请人： Dana How ,  Adi Srinivasan ,  Robert Osann, Jr. ,  Shridhar Mukund

发明人： Dana How ,  Adi Srinivasan ,  Robert Osann, Jr. ,  Shridhar Mukund

IPC分类号： G01R3128

CPC分类号： G01R31/318516

摘要： A system for testing an integrated circuit, and particularly a gate array, is disclosed which includes, prior to coupling the array to form a user-designed circuit, predesigned logic that enables testing of the user-designed circuit. The predesigned logic allows logic blocks in the array to operate in “freeze” mode or to operate in normal mode, where normal mode is defined by the user-designed circuit. When the logic blocks are selected to be frozen, the logic blocks behave as a series of daisy-chained master-slave flip-flops. In normal mode, a logic block can implement combinational, sequential, or other functions and still later be as a master-slave flip-flop. Moreover, each logic block is further equipped for addressable mode control, allowing selected logic blocks to be exercised in isolation once stimulus data is shifted in, simplifying test generation and improving fault coverage.

摘要翻译： 公开了用于测试集成电路，特别是门阵列的系统，其在耦合阵列以形成用户设计的电路之前包括能够测试用户设计的电路的预先设计的逻辑。 预先设计的逻辑允许阵列中的逻辑块以“冻结”模式运行或在正常模式下运行，其中正常模式由用户设计的电路定义。 当逻辑块被选择为冻结时，逻辑块表现为一系列菊花链主主机触发器。 在正常模式下，逻辑块可以实现组合，顺序或其他功能，并且稍后将作为主从触发器。 此外，每个逻辑块进一步配置为可寻址模式控制，允许一旦激励数据被移位，孤立地选择逻辑块，简化测试生成并提高故障覆盖。

公开(公告)号：US06954917B2

公开(公告)日：2005-10-11

申请号：US10460343

申请日：2003-06-11

申请人： Dana How ,  Adi Srinivasan ,  Abbas El Gamal

发明人： Dana How ,  Adi Srinivasan ,  Abbas El Gamal

IPC分类号： G06F1/10 ,  G06F17/50 ,  H03K19/173 ,  H03K19/177

CPC分类号： G06F1/10 ,  G06F17/5045 ,  G06F17/5068 ,  H03K19/1737 ,  H03K19/17704 ,  H03K19/17796

摘要： A method for forming an application specific integrated circuit, comprises receiving a circuit design for the application specific integrated circuit from a designer; performing an initial place and route layout of the circuit design which leaves a group of buffer modules unused, based upon a partially predesigned integrated circuit, in which the partially predesigned integrated circuit includes a plurality of logic modules and a plurality of buffer modules uniformly distributed amongst the logic modules; evaluating load and timing characteristics for the initial place and route layout of the circuit design; and integrating buffer modules from the group of unused buffer modules into the circuit design, based on the load and timing characteristics evaluated. A gate array, for forming the application specific integrated circuit in accordance with the invention includes a matrix of function blocks capable of being configured to implement combinational, sequential, and memory modes of operation, as well as providing tri-state drivers and buffers in useful numbers.

摘要翻译： 一种用于形成专用集成电路的方法，包括从设计者接收针对专用集成电路的电路设计; 基于部分预先设计的集成电路执行留下一组缓冲器模块的电路设计的初始位置和路线布局，其中部分预先设计的集成电路包括多个逻辑模块和均匀分布在 逻辑模块; 评估电路设计的初始位置和路线布局的负载和时序特性; 并根据评估的负载和时序特性，将来自一组未使用的缓冲器模块的缓冲器模块集成到电路设计中。 用于形成根据本发明的专用集成电路的门阵列包括能够被配置为实现组合，顺序和存储器操作模式的功能块矩阵，以及提供有用的三态驱动器和缓冲器 数字。

公开(公告)号：US06242767B1

公开(公告)日：2001-06-05

申请号：US08966946

申请日：1997-11-10

申请人： Dana How ,  Adi Srinivasan ,  Abbas El Gamal

发明人： Dana How ,  Adi Srinivasan ,  Abbas El Gamal

IPC分类号： H01L2710

CPC分类号： H01L27/0207 ,  H01L27/118

摘要： A customizable ASIC routing architecture is provided. The architecture utilizes the uppermost metal layers of an ASIC composed of an array of function blocks for routing among function blocks while lower layers are used for local interconnections within the function blocks. The second-to-uppermost metal layer is fixed and generally includes a plurality of parallel segmented conductors extending in a first direction. The uppermost metal layer is customizable in a predesignated manner. Metal in the uppermost metal layer is selectively placed in tracks, which are substantially perpendicular to the segmented conductors in the layer below. Vias are provided between the two uppermost layers. One embodiment of the invention permits one-mask customization of an ASIC.

摘要翻译： 提供可定制的ASIC路由架构。 该架构使用由功能块阵列组成的ASIC的最上层金属层，用于在功能块之间路由，而较低层用于功能块内的本地互连。 第二至第三金属层是固定的，并且通常包括沿第一方向延伸的多个平行的分段导体。 最上层的金属层可以预先指定的方式定制。 最上层金属层中的金属被选择性地放置在跟下面的层中基本上垂直于分段导体的轨道中。 在两个最上层之间提供通孔。 本发明的一个实施例允许ASIC的单掩模定制。

公开(公告)号：US6014038A

公开(公告)日：2000-01-11

申请号：US821475

申请日：1997-03-21

申请人： Dana How ,  Adi Srinivasan ,  Abbas El Gamal

发明人： Dana How ,  Adi Srinivasan ,  Abbas El Gamal

IPC分类号： G06F1/10 ,  G06F17/50 ,  H03K19/173 ,  H03K19/177 ,  G06F7/38

CPC分类号： G06F1/10 ,  G06F17/5045 ,  G06F17/5068 ,  H03K19/1737 ,  H03K19/17704 ,  H03K19/17796

摘要： A gate array in accordance with the invention includes a matrix of function blocks capable of being configured to implement combinational, sequential, and memory modes of operation, as well as providing tri-state drivers and buffers in useful numbers. The function block includes a logic circuit with a first bit storage unit, which is selectively configurable to behave as combinational logic or to store a first bit, and a second bit storage unit, which is also selectively configurable to behave as combinational logic or to store a second bit. The matrix of function blocks in accordance with the invention is also useful to properly distribute clocks throughout the gate array.

公开(公告)号：US06690194B1

公开(公告)日：2004-02-10

申请号：US09414697

申请日：1999-10-07

申请人： Dana How ,  Adi Srinivasan ,  Abbas El Gamal

发明人： Dana How ,  Adi Srinivasan ,  Abbas El Gamal

IPC分类号： H03K19177

CPC分类号： G06F1/10 ,  G06F17/5045 ,  G06F17/5068 ,  H03K19/1737 ,  H03K19/17704 ,  H03K19/17796

摘要： A gate array in accordance with the invention includes a matrix of function blocks capable of being configured to implement combinational, sequential, and memory modes of operation, as well as providing tri-state drivers and buffers in useful numbers. The function block includes a logic circuit with a first bit storage unit, which is selectively configurable to behave as combinational logic or to store a first bit, and a second bit storage unit, which is also selectively configurable to behave as combinational logic or to store a second bit. The matrix of function blocks in accordance with the invention is also useful to properly distribute clocks throughout the gate array.

摘要翻译： 根据本发明的门阵列包括能够被配置为实现组合，顺序和存储器操作模式的功能块矩阵，以及提供有用数字的三态驱动器和缓冲器。 功能块包括具有第一位存储单元的逻辑电路，其可选择性地配置为表现为组合逻辑或存储第一位，以及第二位存储单元，其也可选择性地配置为表现为组合逻辑或存储 一秒钟 根据本发明的功能块的矩阵对于在整个门阵列中正确分配时钟也是有用的。

公开(公告)号：US5367482A

公开(公告)日：1994-11-22

申请号：US110682

申请日：1993-08-23

申请人： Ta-Pen Guo ,  Adi Srinivasan

发明人： Ta-Pen Guo ,  Adi Srinivasan

IPC分类号： G11C11/412 ,  H03K3/356 ,  G11C11/40

CPC分类号： H03K3/356156 ,  G11C11/412

摘要： A level-shifting static random access memory cell includes a first stage having a first P-Channel MOS transistor having its source connected to a high voltage supply rail, and its drain connected to the drain of a first N-Channel MOS transistor. The source of the first N-Channel MOS transistor is connected to the drain of a second N-Channel MOS transistor. The source of the second N-channel MOS transistor is connected to a VSS power supply rail. A second stage comprises a second P-Channel MOS transistor having its source connected to the high voltage supply rail V.sub.HS, and its drain connected to the drain of a third N-Channel MOS transistor. The source of the third N-Channel MOS transistor is connected to the drain of a fourth N-Channel MOS transistor. The source of the fourth N-channel MOS transistor is connected to VSS. The gates of the first and second P-Channel MOS transistors are cross coupled and the gates of the second and fourth N-Channel MOS transistors are cross coupled. The gates of the first and third N-channel MOS transistors are connected together to power supply rail V.sub.DD, usually 5 volts. The first and second P-channel MOS transistors are formed in an n-well biased at power supply voltage V.sub.HS. A bit line coupled to the drain of the second N-Channel MOS transistor through a fifth N-Channel MOS transistor, having its gate connected to a word line.

摘要翻译： 电平移动静态随机存取存储单元包括具有第一P沟道MOS晶体管的第一级，其第一P沟道MOS晶体管的源极连接到高压电源轨，漏极连接到第一N沟道MOS晶体管的漏极。 第一N沟道MOS晶体管的源极连接到第二N沟道MOS晶体管的漏极。 第二N沟道MOS晶体管的源极连接到VSS电源轨。 第二级包括其源极连接到高压电源轨VHS的第二P沟道MOS晶体管，其漏极连接到第三N沟道MOS晶体管的漏极。 第三N沟道MOS晶体管的源极连接到第四N沟道MOS晶体管的漏极。 第四个N沟道MOS晶体管的源极连接到VSS。 第一和第二P沟道MOS晶体管的栅极交叉耦合，并且第二和第四N沟道MOS晶体管的栅极交叉耦合。 第一和第三N沟道MOS晶体管的栅极连接到电源轨VDD，通常为5伏。 第一和第二P沟道MOS晶体管形成在电压为VHS的n阱偏置中。 通过第五N沟道MOS晶体管耦合到第二N沟道MOS晶体管的漏极的位线，其栅极连接到字线。

公开(公告)号：US5239503A

公开(公告)日：1993-08-24

申请号：US900241

申请日：1992-06-17

申请人： Ta-Pen Guo ,  Adi Srinivasan

发明人： Ta-Pen Guo ,  Adi Srinivasan

IPC分类号： G11C11/412 ,  H03K3/356

CPC分类号： H03K3/356156 ,  G11C11/412

摘要： A level-shifting static random access memory cell includes a first stage having a first P-Channel MOS transistor having its source connected to a high voltage supply rail, and its drain connected to the drain of a first N-Channel MOS transistor. The source of the first N-Channel MOS transistor is connected to the drain of a second N-Channel MOS transistor. The source of the second N-channel MOS transistor is connected to a VSS power supply rail. A second stage comprises a second P-Channel MOS transistor having its source connected to the high voltage supply rail V.sub.HS, and its drain connected to the drain of a third N-Channel MOS transistor. The source of the third N-Channel MOS transistor is connected to the drain of a fourth N-Channel MOS transistor. The source of the fourth N-channel MOS transistor is connected to VSS. The gates of the first and second P-Channel MOS transistors are cross coupled and the gates of the second and fourth N-Channel MOS transistors are cross coupled. The gates of the first and third N-channel MOS transistors are connected together to power supply rail V.sub.DD, usually 5 volts. The first and second P-channel MOS transistors are formed in an n-well biased at power supply voltage V.sub.HS. A bit line coupled to the drain of the second N-Channel MOS transistor through a fifth N-Channel MOS transistor, having its gate connected to a word line.

公开(公告)号：US06701507B1

公开(公告)日：2004-03-02

申请号：US10022751

申请日：2001-12-14

申请人： Adi Srinivasan

发明人： Adi Srinivasan

IPC分类号： G06F1750

CPC分类号： G06F17/5068

摘要： A method for computing a position for a zero-skew driver insertion point in an area occupied by nodes driven by the driver is described. The zero-skew driver insertion point is the position in the area where the spread of the signal arrival times at the nodes driven by the driver is minimized. The method includes: expressing a function describing a distance from each of the nodes to the zero-skew driver insertion point, expressing the variance of the function, minimizing the variance of the function, and solving an equation representative of the minimization of the variance of the function to determine the position of the zero-skew driver insertion point. In one embodiment, the minimizing the variance of the function includes: taking a first derivative of the function with respect to the distance, and setting the first derivative of the function to zero.

摘要翻译： 描述了用于计算由驾驶员驱动的节点占据的区域中的零倾斜驱动器插入点的位置的方法。 零偏移驱动器插入点是在由驱动器驱动的节点处的信号到达时间的扩展最小化的区域中的位置。 该方法包括：表达描述从每个节点到零偏移驱动器插入点的距离的函数，表示函数的方差，最小化函数的方差，以及求解表示方差最小化的方程 确定零倾斜驱动器插入点位置的功能。 在一个实施例中，使函数的方差最小化包括：相对于距离获取函数的一阶导数，并将函数的一阶导数设置为零。

公开(公告)号：US06698006B1

公开(公告)日：2004-02-24

申请号：US10023329

申请日：2001-12-14

申请人： Adi Srinivasan ,  David L. Allen

发明人： Adi Srinivasan ,  David L. Allen

IPC分类号： G06F1750

CPC分类号： G06F1/10 ,  G06F17/5068 ,  G06F2217/62

摘要： A clock tree insertion method for distributing a clock signal in an integrated circuit design includes providing a physical design representative of the integrated circuit design, specifying a location for a root node of the clock tree in the physical design, constructing an array of buffers as the clock tree where the array of buffers is constructed to minimize the maximum insertion delay from the root node to the clock signal endpoints and to meet a predefined maximum insertion delay constraint, identifying locations in the clock tree where clock skew violations occur and correcting the clock skew violations by introducing delay at buffer locations in the clock tree having the fastest clock signal arrival times, and identifying locations in the clock tree where minimum insertion delay violations occur and correcting the minimum insertion delay violations by slowing down the arrival times of clock signal endpoints of the clock tree.

摘要翻译： 用于在集成电路设计中分配时钟信号的时钟树插入方法包括提供代表集成电路设计的物理设计，在物理设计中指定时钟树的根节点的位置，构建缓冲器阵列作为 时钟树，其中缓冲器阵列被构造为最小化从根节点到时钟信号端点的最大插入延迟，并且满足预定义的最大插入延迟约束，识别时钟树中发生时钟偏斜违规的位置并校正时钟偏差 通过在具有最快时钟信号到达时间的时钟树中的缓冲器位置处引入延迟，以及识别发生最小插入延迟违规的时钟树中的位置并通过减慢最小插入延迟违规来校正最小插入延迟违反，从而延迟时钟信号端点的到达时间 时钟树。