公开(公告)号：US06223313B1

公开(公告)日：2001-04-24

申请号：US08985790

申请日：1997-12-05

申请人： Dana How ,  Adi Srinivasan ,  Robert Osann ,  Shridhar Mukund

发明人： Dana How ,  Adi Srinivasan ,  Robert Osann ,  Shridhar Mukund

IPC分类号： G01R3128

CPC分类号： G01R31/318516

摘要： A system for testing an integrated circuit, and particularly a gate array, is disclosed which includes, prior to coupling the array to form a user-designed circuit, predesigned logic that enables testing of the user-designed circuit. The predesigned logic allows logic blocks in the array to operate in “freeze” mode or to operate in normal mode, where normal mode is defined by the user-designed circuit. Much of the same circuitry in the logic blocks is, in fact, used in both modes of operation, thus minimizing circuitry added due to test. When the logic blocks are selected to be frozen, the logic blocks behave as a series of daisy-chained master-slave flip-flops. Stimulus data is shifted into the array and captured data is shifted out of the array through the daisy-chained flip-flops. Nonetheless, when data is shifted into and out of the daisy-chained flip-flops, the master latch and the slave latch of each flip-flop can be set to receive independent values and the data captured by each of the master and slave latches can be independently shifted out and analyzed. Although when frozen, the logic blocks behave as daisy-chained flip-flops, use of the logic blocks for testing purposes does not depend upon placement of sequential elements in the user-designed circuit in the logic blocks. In other words, in normal mode, a logic block can implement combinational, sequential, or other functions and still later be used to drive out stimulus values or capture results. Moreover, each logic block is further equipped for addressable mode control, allowing selected logic blocks to be exercised in isolation once stimulus data is shifted in, simplifying test generation and improving fault coverage. Using a logic block in accordance with the invention results in a high level of fault coverage, while placing few limitations on the user's circuit design.

摘要翻译： 公开了用于测试集成电路，特别是门阵列的系统，其包括在耦合阵列以形成用户设计的电路之前，预先设计的逻辑，其能够测试用户设计的电路。 预先设计的逻辑允许阵列中的逻辑块以“冻结”模式运行或在正常模式下运行，其中正常模式由用户设计的电路定义。 事实上，逻辑块中的大部分相同的电路用于两种工作模式，从而最小化由于测试而添加的电路。 当逻辑块被选择为冻结时，逻辑块表现为一系列菊花链主主机触发器。 激励数据移入阵列，捕获的数据通过菊花链式触发器从阵列中移出。 然而，当数据被移入和移出菊花链触发器时，每个触发器的主锁存器和从锁存器可被设置为接收独立的值，并且由每个主锁存器和从锁存器捕获的数据可以 独立移出并分析。 尽管在冻结时，逻辑块表现为菊花链式触发器，但用于测试目的的逻辑块的使用并不取决于逻辑块中用户设计的电路中顺序元件的位置。 换句话说，在正常模式下，逻辑块可以实现组合，顺序或其他功能，并且稍后可用于驱出刺激值或捕获结果。 此外，每个逻辑块进一步配置为可寻址模式控制，允许一旦激励数据被移位，孤立地选择逻辑块，简化测试生成并提高故障覆盖。 使用根据本发明的逻辑块导致高水平的故障覆盖，同时对用户的电路设计几乎没有限制。

公开(公告)号：US06611932B2

公开(公告)日：2003-08-26

申请号：US10056686

申请日：2002-01-24

申请人： Dana How ,  Adi Srinivasan ,  Robert Osann, Jr. ,  Shridhar Mukund

发明人： Dana How ,  Adi Srinivasan ,  Robert Osann, Jr. ,  Shridhar Mukund

IPC分类号： G01R3128

CPC分类号： G01R31/318516

摘要： A system for testing an integrated circuit, and particularly a gate array, is disclosed which includes, prior to coupling the array to form a user-designed circuit, predesigned logic that enables testing of the user-designed circuit. The predesigned logic allows logic blocks in the array to operate in “freeze” mode or to operate in normal mode, where normal mode is defined by the user-designed circuit. When the logic blocks are selected to be frozen, the logic blocks behave as a series of daisy-chained master-slave flip-flops. In normal mode, a logic block can implement combinational, sequential, or other functions and still later be as a master-slave flip-flop. Moreover, each logic block is further equipped for addressable mode control, allowing selected logic blocks to be exercised in isolation once stimulus data is shifted in, simplifying test generation and improving fault coverage.

摘要翻译： 公开了用于测试集成电路，特别是门阵列的系统，其在耦合阵列以形成用户设计的电路之前包括能够测试用户设计的电路的预先设计的逻辑。 预先设计的逻辑允许阵列中的逻辑块以“冻结”模式运行或在正常模式下运行，其中正常模式由用户设计的电路定义。 当逻辑块被选择为冻结时，逻辑块表现为一系列菊花链主主机触发器。 在正常模式下，逻辑块可以实现组合，顺序或其他功能，并且稍后将作为主从触发器。 此外，每个逻辑块进一步配置为可寻址模式控制，允许一旦激励数据被移位，孤立地选择逻辑块，简化测试生成并提高故障覆盖。

公开(公告)号：US6014038A

公开(公告)日：2000-01-11

申请号：US821475

申请日：1997-03-21

申请人： Dana How ,  Adi Srinivasan ,  Abbas El Gamal

发明人： Dana How ,  Adi Srinivasan ,  Abbas El Gamal

IPC分类号： G06F1/10 ,  G06F17/50 ,  H03K19/173 ,  H03K19/177 ,  G06F7/38

CPC分类号： G06F1/10 ,  G06F17/5045 ,  G06F17/5068 ,  H03K19/1737 ,  H03K19/17704 ,  H03K19/17796

摘要： A gate array in accordance with the invention includes a matrix of function blocks capable of being configured to implement combinational, sequential, and memory modes of operation, as well as providing tri-state drivers and buffers in useful numbers. The function block includes a logic circuit with a first bit storage unit, which is selectively configurable to behave as combinational logic or to store a first bit, and a second bit storage unit, which is also selectively configurable to behave as combinational logic or to store a second bit. The matrix of function blocks in accordance with the invention is also useful to properly distribute clocks throughout the gate array.

公开(公告)号：US06690194B1

公开(公告)日：2004-02-10

申请号：US09414697

申请日：1999-10-07

申请人： Dana How ,  Adi Srinivasan ,  Abbas El Gamal

发明人： Dana How ,  Adi Srinivasan ,  Abbas El Gamal

IPC分类号： H03K19177

CPC分类号： G06F1/10 ,  G06F17/5045 ,  G06F17/5068 ,  H03K19/1737 ,  H03K19/17704 ,  H03K19/17796

摘要： A gate array in accordance with the invention includes a matrix of function blocks capable of being configured to implement combinational, sequential, and memory modes of operation, as well as providing tri-state drivers and buffers in useful numbers. The function block includes a logic circuit with a first bit storage unit, which is selectively configurable to behave as combinational logic or to store a first bit, and a second bit storage unit, which is also selectively configurable to behave as combinational logic or to store a second bit. The matrix of function blocks in accordance with the invention is also useful to properly distribute clocks throughout the gate array.

摘要翻译： 根据本发明的门阵列包括能够被配置为实现组合，顺序和存储器操作模式的功能块矩阵，以及提供有用数字的三态驱动器和缓冲器。 功能块包括具有第一位存储单元的逻辑电路，其可选择性地配置为表现为组合逻辑或存储第一位，以及第二位存储单元，其也可选择性地配置为表现为组合逻辑或存储 一秒钟 根据本发明的功能块的矩阵对于在整个门阵列中正确分配时钟也是有用的。

公开(公告)号：US06242767B1

公开(公告)日：2001-06-05

申请号：US08966946

申请日：1997-11-10

申请人： Dana How ,  Adi Srinivasan ,  Abbas El Gamal

发明人： Dana How ,  Adi Srinivasan ,  Abbas El Gamal

IPC分类号： H01L2710

CPC分类号： H01L27/0207 ,  H01L27/118

摘要： A customizable ASIC routing architecture is provided. The architecture utilizes the uppermost metal layers of an ASIC composed of an array of function blocks for routing among function blocks while lower layers are used for local interconnections within the function blocks. The second-to-uppermost metal layer is fixed and generally includes a plurality of parallel segmented conductors extending in a first direction. The uppermost metal layer is customizable in a predesignated manner. Metal in the uppermost metal layer is selectively placed in tracks, which are substantially perpendicular to the segmented conductors in the layer below. Vias are provided between the two uppermost layers. One embodiment of the invention permits one-mask customization of an ASIC.

摘要翻译： 提供可定制的ASIC路由架构。 该架构使用由功能块阵列组成的ASIC的最上层金属层，用于在功能块之间路由，而较低层用于功能块内的本地互连。 第二至第三金属层是固定的，并且通常包括沿第一方向延伸的多个平行的分段导体。 最上层的金属层可以预先指定的方式定制。 最上层金属层中的金属被选择性地放置在跟下面的层中基本上垂直于分段导体的轨道中。 在两个最上层之间提供通孔。 本发明的一个实施例允许ASIC的单掩模定制。

公开(公告)号：US06954917B2

公开(公告)日：2005-10-11

申请号：US10460343

申请日：2003-06-11

申请人： Dana How ,  Adi Srinivasan ,  Abbas El Gamal

发明人： Dana How ,  Adi Srinivasan ,  Abbas El Gamal

IPC分类号： G06F1/10 ,  G06F17/50 ,  H03K19/173 ,  H03K19/177

CPC分类号： G06F1/10 ,  G06F17/5045 ,  G06F17/5068 ,  H03K19/1737 ,  H03K19/17704 ,  H03K19/17796

摘要： A method for forming an application specific integrated circuit, comprises receiving a circuit design for the application specific integrated circuit from a designer; performing an initial place and route layout of the circuit design which leaves a group of buffer modules unused, based upon a partially predesigned integrated circuit, in which the partially predesigned integrated circuit includes a plurality of logic modules and a plurality of buffer modules uniformly distributed amongst the logic modules; evaluating load and timing characteristics for the initial place and route layout of the circuit design; and integrating buffer modules from the group of unused buffer modules into the circuit design, based on the load and timing characteristics evaluated. A gate array, for forming the application specific integrated circuit in accordance with the invention includes a matrix of function blocks capable of being configured to implement combinational, sequential, and memory modes of operation, as well as providing tri-state drivers and buffers in useful numbers.

摘要翻译： 一种用于形成专用集成电路的方法，包括从设计者接收针对专用集成电路的电路设计; 基于部分预先设计的集成电路执行留下一组缓冲器模块的电路设计的初始位置和路线布局，其中部分预先设计的集成电路包括多个逻辑模块和均匀分布在 逻辑模块; 评估电路设计的初始位置和路线布局的负载和时序特性; 并根据评估的负载和时序特性，将来自一组未使用的缓冲器模块的缓冲器模块集成到电路设计中。 用于形成根据本发明的专用集成电路的门阵列包括能够被配置为实现组合，顺序和存储器操作模式的功能块矩阵，以及提供有用的三态驱动器和缓冲器 数字。

公开(公告)号：US06613611B1

公开(公告)日：2003-09-02

申请号：US09747129

申请日：2000-12-22

申请人： Dana How ,  Robert Osann, Jr. ,  Eric Dellinger

发明人： Dana How ,  Robert Osann, Jr. ,  Eric Dellinger

IPC分类号： H01L2182

CPC分类号： H01L27/118

摘要： A customizable ASIC routing architecture is provided. The architecture utilizes the uppermost metal layers of an ASIC composed of an array of function blocks for routing among function blocks while lower layers are used for local interconnections within the function blocks. The second-to-uppermost metal layer is fixed and generally includes a plurality of parallel segmented conductors extending in a first direction. The uppermost metal layer is customizable in a predesignated manner. Metal in the uppermost metal layer is selectively placed in tracks, which are substantially perpendicular to the segmented conductors in the layer below. Vias are provided between the two uppermost layers. One embodiment of the invention permits one-mask customization of an ASIC. Other embodiments allow a determination to be made of the ideal number of custom mask steps, taking into consideration performance, cost, time, and routability.

摘要翻译： 提供可定制的ASIC路由架构。 该架构使用由功能块阵列组成的ASIC的最上层金属层，用于在功能块之间路由，而较低层用于功能块内的本地互连。 第二至第三金属层是固定的，并且通常包括沿第一方向延伸的多个平行的分段导体。 最上层的金属层可以预先指定的方式定制。 最上层金属层中的金属被选择性地放置在跟下面的层中基本上垂直于分段导体的轨道中。 在两个最上层之间提供通孔。 本发明的一个实施例允许ASIC的单掩模定制。 考虑到性能，成本，时间和可路由性，其他实施例允许确定理想数量的定制掩模步骤。

公开(公告)号：US08405418B1

公开(公告)日：2013-03-26

申请号：US13107899

申请日：2011-05-14

申请人： Dana How ,  Godfrey P. D'Souza ,  Malcolm J. Wing ,  Colin N. Murphy ,  Arun Jangity

发明人： Dana How ,  Godfrey P. D'Souza ,  Malcolm J. Wing ,  Colin N. Murphy ,  Arun Jangity

IPC分类号： H03K19/173

CPC分类号： G06F13/4022 ,  Y02D10/14 ,  Y02D10/151

摘要： A bus structure providing pipelined busing of data between logic circuits and special-purpose circuits of an integrated circuit, the bus structure including a network of pipelined conductors, and connectors selectively joining the pipelined conductors between the special-purpose circuits, other pipelined connectors, and the logic circuits.

公开(公告)号：US09165931B1

公开(公告)日：2015-10-20

申请号：US14187185

申请日：2014-02-21

申请人： Herman Schmit ,  David Lewis ,  Michael D. Hutton ,  Dana How ,  Andy L. Lee

发明人： Herman Schmit ,  David Lewis ,  Michael D. Hutton ,  Dana How ,  Andy L. Lee

IPC分类号： H01L27/115 ,  G06F17/50 ,  H01L27/105

CPC分类号： G06F17/5054 ,  G06F15/7867 ,  H01L27/115 ,  H03K19/17728

摘要： An integrated circuit (IC) includes a substrate that is common to the IC and variants of the IC. The IC also includes a first set of interconnect layers fabricated above the substrate. The first set of interconnect layers is used to couple programmable interconnect of the IC to a first circuit in the substrate. The IC further includes a second set of interconnect layers fabricated above the substrate. The second set of interconnect layers is used to differentiate features of the IC from variants of the IC by selectively coupling the programmable interconnect to a second circuit in the substrate.

摘要翻译： 集成电路（IC）包括IC的通用基板和IC的变体。 IC还包括在衬底上方制造的第一组互连层。 第一组互连层用于将IC的可编程互连件耦合到衬底中的第一电路。 IC还包括在衬底上方制造的第二组互连层。 第二组互连层用于通过选择性地将可编程互连连接到衬底中的第二电路来区分IC的特征与IC的变体。

公开(公告)号：US07944236B2

公开(公告)日：2011-05-17

申请号：US12855466

申请日：2010-08-12

申请人： Dana How ,  Godfrey P. D'Souza ,  Malcolm J. Wing ,  Colin N. Murphy ,  Arun Jangity

发明人： Dana How ,  Godfrey P. D'Souza ,  Malcolm J. Wing ,  Colin N. Murphy ,  Arun Jangity

IPC分类号： H03K19/173

CPC分类号： G06F13/4022 ,  Y02D10/14 ,  Y02D10/151

摘要： A bus structure providing pipelined busing of data between logic circuits and special-purpose circuits of an integrated circuit, the bus structure including a network of pipelined conductors, and connectors selectively joining the pipelined conductors between the special-purpose circuits, other pipelined connectors, and the logic circuits.