公开(公告)号：US20050007145A1

公开(公告)日：2005-01-13

申请号：US10616845

申请日：2003-07-10

申请人： Daniel Dreps ,  Frank Ferraiolo ,  Anand Haridass ,  Bao Truong

发明人： Daniel Dreps ,  Frank Ferraiolo ,  Anand Haridass ,  Bao Truong

IPC分类号： H03K19/003

CPC分类号： H04L25/0278 ,  H04L25/0296

摘要： A termination network has multiple resistors forming multiple voltage dividers with a common node. Half of the resistors are coupled to the positive power supply voltage with P channel field effect transistors (PFETs) and the other half are coupled to the negative or ground power supply voltage with N channel FETs (NFETs). Logic signals are used to control the gates of the FETs. By modifying which FETs are ON, the termination network can be selectively controlled to produce various offset levels with the same impedance level. The impedance levels may also be modified while maintaining the same offset level. A delay circuit may be selectively employed to feedback control signals after a selected delay time to adjust the threshold level to dynamically or statically optimize signal reception.

公开(公告)号：US20080074998A1

公开(公告)日：2008-03-27

申请号：US11948620

申请日：2007-11-30

申请人： WIREN BECKER ,  Daniel Dreps ,  Frank Ferraiolo ,  Anand Haridass ,  Robert Reese

发明人： WIREN BECKER ,  Daniel Dreps ,  Frank Ferraiolo ,  Anand Haridass ,  Robert Reese

IPC分类号： G01R31/08 ,  G06F11/00

CPC分类号： H01L22/22 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method, apparatus, and computer instructions for managing a set of signal paths for a chip. A defective signal path within the set of signal paths for the chip is detected. Signals are re-routed through the set of signal paths such that the defective signal path is removed from the set of signal paths and sending signals using remaining data signal paths in the set of signal paths and using an extra signal path in response to detecting the defective signal path.

摘要翻译： 一种用于管理用于芯片的一组信号路径的方法，装置和计算机指令。 检测用于芯片的信号路径集合内的有缺陷的信号路径。 信号通过一组信号路径重新路由，使得有缺陷的信号路径从信号路径集合中移除，并使用信号路径组中的剩余数据信号路径发送信号，并且响应于检测到的信号路径 有缺陷的信号路径。

公开(公告)号：US20070046389A1

公开(公告)日：2007-03-01

申请号：US11209549

申请日：2005-08-23

申请人： Daniel Dreps ,  Anand Haridass ,  Bao Truong ,  Joel Ziegelbein

发明人： Daniel Dreps ,  Anand Haridass ,  Bao Truong ,  Joel Ziegelbein

IPC分类号： H01P5/00

CPC分类号： H04L25/0272 ,  H04B3/32

摘要： Signaling between two or more ICs use a signaling scheme wherein a reference signal is generated at the driver side and the receiver side. The driver side reference signal is coupled to the receiver side reference signal with a transmission line channel forming a reference channel. Data signal channels are paired with a reference channel between each two adjacent data channels. Adjacent pairs of data signal channels are each separated with an empty wiring channel. The paired data signals are received in one input of a differential receiver. The reference signal of the reference channel between the two paired data channels is coupled to the other input of the two differential receivers. Coupling from the paired data channels to the reference channel appears a common mode noise and is rejected by the differential receivers. The number of channels is reduced from a full differential signaling scheme.

摘要翻译： 两个或多个IC之间的信令使用信令方案，其中在驱动器侧和接收机侧产生参考信号。 驱动器侧参考信号通过形成参考通道的传输线路通道耦合到接收机侧参考信号。 数据信号通道与每两个相邻数据通道之间的参考通道配对。 相邻的数据信号通道对都分开一个空的布线通道。 成对的数据信号在差分接收机的一个输入端被接收。 两个成对数据信道之间的参考信道的参考信号耦合到两个差分接收机的另一个输入端。 从配对数据通道耦合到参考通道出现共模噪声，并被差分接收器拒绝。 信道数量从全差分信令方案中减少。

公开(公告)号：US20050253622A1

公开(公告)日：2005-11-17

申请号：US10845568

申请日：2004-05-13

申请人： Daniel M. Dreps ,  Anand Haridass ,  Bao Truong

发明人： Daniel M. Dreps ,  Anand Haridass ,  Bao Truong

IPC分类号： H03K17/16 ,  H04L25/06 ,  H04L25/45

CPC分类号： H04L25/061 ,  H04L25/45

摘要： Two or more integrated circuit (IC) chips are separated by a significant distance relative to their communication frequency such that pseudo-differential signaling is used to improve signal detection. A derived reference voltage is generated that tracks the variations of the driver and receiver side power supply variations that normally reduce noise margins. The derived reference voltage is filtered to reduce high frequency response and coupled as the reference to differential receivers used to detect the logic levels of the communication signals.

摘要翻译： 两个或多个集成电路（IC）芯片相对于它们的通信频率被隔开相当长的距离，使得伪差分信号用于改善信号检测。 产生导出的参考电压，其跟踪通常降低噪声容限的驱动器和接收机侧电源变化的变化。 导出的参考电压被滤波以降低高频响应并作为用于检测通信信号的逻辑电平的差分接收器的参考而耦合。

公开(公告)号：US20080092101A1

公开(公告)日：2008-04-17

申请号：US11951705

申请日：2007-12-06

申请人： Anand Haridass ,  Andreas Huber ,  Bao Truong ,  Roger Weekly

发明人： Anand Haridass ,  Andreas Huber ,  Bao Truong ,  Roger Weekly

IPC分类号： G06F17/50

CPC分类号： H01L23/50 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  Y10T29/49155 ,  Y10T29/49163 ,  H01L2924/00

摘要： A mechanism for reducing the vertical cross-talk interference experienced in signal lines due to the inductive affects from signal lines in other signal planes of a multi-layer ceramic package is provided. With the apparatus and method, one or more vias in the multi-layer ceramic package may be removed from the structure to provide area through which an offset of the signal lines may pass. Because these offsets of the signal lines exist in parallel planes above or below each other, with no ground lines existing directly between these signal line offsets, a capacitive cross-talk is introduced into the signal lines. This capacitive cross-talk is opposite in polarity to the inductive cross-talk already experienced by the signal lines. As a result, the capacitive cross-talk tends to negate or reduce the inductive cross-talk thereby reducing the far end noise in the signal line.

摘要翻译： 提供了一种用于减少由于来自多层陶瓷封装的其它信号面中的信号线的感应影响而在信号线中遭受的垂直串扰干扰的机制。 利用该装置和方法，多层陶瓷封装中的一个或多个通孔可以从结构中移除以提供信号线的偏移通过的区域。 由于信号线的这些偏移存在于彼此之上或之下的并行平面中，在这些信号线偏移之间没有直接存在接地线，所以在信号线中引入电容性串扰。 该电容串扰与信号线已经经历的电感串扰的极性相反。 结果，电容串扰倾向于消除或减少电感串扰，从而减少信号线中的远端噪声。

公开(公告)号：US20060215769A1

公开(公告)日：2006-09-28

申请号：US11086718

申请日：2005-03-22

申请人： Anand Haridass ,  Bao Truong ,  Joel Ziegelbein

发明人： Anand Haridass ,  Bao Truong ,  Joel Ziegelbein

IPC分类号： H04L25/00

CPC分类号： H04L25/0274 ,  H03F3/45197 ,  H03F2200/543 ,  H03F2203/45488

摘要： A driver circuit is configured as a frequency compensated differential amplifier having one input coupled to a first data signal and a second input coupled to a second data signal. Each stage of the differential amplifier is biased with a current source. The driver circuit generates a first output signal coupled to the input of a first transmission line and a second output signal coupled to the input of a second transmission line. The first and second output signals are generated as the difference between the first and second data signals amplified by a compensated gain. A compensation network that attenuates the low frequency components of the input signals relative to the high frequency components is coupled between current sources biasing the differential amplifier. The outputs of the first and second transmission lines are coupled to the inputs of a differential receiver that may or may not be frequency compensated.

公开(公告)号：US20080087457A1

公开(公告)日：2008-04-17

申请号：US11951646

申请日：2007-12-06

申请人： Anand Haridass ,  Andreas Huber ,  Bao Truong ,  Roger Weekly

发明人： Anand Haridass ,  Andreas Huber ,  Bao Truong ,  Roger Weekly

IPC分类号： H05K7/06

CPC分类号： H01L23/50 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  Y10T29/49155 ,  Y10T29/49163 ,  H01L2924/00

摘要： A mechanism for reducing the vertical cross-talk interference experienced in signal lines due to the inductive affects from signal lines in other signal planes of a multi-layer ceramic package is provided. With the apparatus and method, one or more vias in the multi-layer ceramic package may be removed from the structure to provide area through which an offset of the signal lines may pass. Because these offsets of the signal lines exist in parallel planes above or below each other, with no ground lines existing directly between these signal line offsets, a capacitive cross-talk is introduced into the signal lines. This capacitive cross-talk is opposite in polarity to the inductive cross-talk already experienced by the signal lines. As a result, the capacitive cross-talk tends to negate or reduce the inductive cross-talk thereby reducing the far end noise in the signal line.

公开(公告)号：US20070239387A1

公开(公告)日：2007-10-11

申请号：US11278848

申请日：2006-04-06

申请人： Daniel Douriet ,  Anand Haridass ,  Andreas Huber ,  Colm O'Reilly ,  Bao Truong ,  Roger Weekly

发明人： Daniel Douriet ,  Anand Haridass ,  Andreas Huber ,  Colm O'Reilly ,  Bao Truong ,  Roger Weekly

IPC分类号： G06F19/00

CPC分类号： G01R19/16552

摘要： An apparatus and method are provided for monitoring the voltage available in each domain of multiple voltage domains of a partitioned electronic chip. In embodiments of the invention, only a single pair of C4 pins is required for all voltage monitoring activity. One useful embodiment is directed to apparatus for monitoring the level of voltage associated with each domain in a partitioned chip. The apparatus comprises a single conductive link coupled to the chip, and further comprises a domain selection network having a single output and a plurality of switchable inputs, the output being connected to the single conductive link, and two inputs being connected to monitor respective voltage levels of two of the plurality of voltage domains. A control mechanism is disposed to operate the selection network, in order to selectively connect one of the inputs to the single conductive link, and a sensor device external to the electronic chip is connected to measure the monitored respective voltage levels of two of the plurality of voltage domains using the single conductive link.

摘要翻译： 提供了一种用于监视分区电子芯片的多个电压域的每个域中可用电压的装置和方法。 在本发明的实施例中，对于所有电压监视活动，仅需要一对C4引脚。 一个有用的实施例涉及用于监视与分区芯片中的每个域相关联的电压电平的装置。 该装置包括耦合到芯片的单个导电链路，并且还包括具有单个输出和多个可切换输入的域选择网络，该输出连接到单个导电链路，并且两个输入端被连接以监视相应的电压电平 的多个电压域中的两个。 设置控制机构以操作选择网络，以便选择性地将输入中的一个连接到单个导电链路，并且电子芯片外部的传感器装置被连接以测量所监视的相应的多个 电压域使用单个导电链路。

公开(公告)号：US20060272851A1

公开(公告)日：2006-12-07

申请号：US11146441

申请日：2005-06-06

申请人： Anand Haridass ,  Andreas Huber ,  Bao Truong ,  Roger Weekly

发明人： Anand Haridass ,  Andreas Huber ,  Bao Truong ,  Roger Weekly

IPC分类号： H05K7/06

CPC分类号： H01L23/50 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  Y10T29/49155 ,  Y10T29/49163 ,  H01L2924/00

摘要： A mechanism for reducing the vertical cross-talk interference experienced in signal lines due to the inductive affects from signal lines in other signal planes of a multi-layer ceramic package is provided. With the apparatus and method, one or more vias in the multi-layer ceramic package may be removed from the structure to provide area through which an offset of the signal lines may pass. Because these offsets of the signal lines exist in parallel planes above or below each other, with no ground lines existing directly between these signal line offsets, a capacitive cross-talk is introduced into the signal lines. This capacitive cross-talk is opposite in polarity to the inductive cross-talk already experienced by the signal lines. As a result, the capacitive cross-talk tends to negate or reduce the inductive cross-talk thereby reducing the far end noise in the signal line.

摘要翻译： 提供了一种用于减少由于来自多层陶瓷封装的其它信号面中的信号线的感应影响而在信号线中遭受的垂直串扰干扰的机制。 利用该装置和方法，多层陶瓷封装中的一个或多个通孔可以从结构中移除以提供信号线偏移通过的区域。 由于信号线的这些偏移存在于彼此之上或之下的并行平面中，在这些信号线偏移之间没有直接存在接地线，所以在信号线中引入电容性串扰。 该电容串扰与信号线已经经历的电感串扰的极性相反。 结果，电容串扰倾向于消除或减少电感串扰，从而减少信号线中的远端噪声。

公开(公告)号：US20070046335A1

公开(公告)日：2007-03-01

申请号：US11211955

申请日：2005-08-25

申请人： Wiren Becker ,  Anand Haridass ,  Bao Truong

发明人： Wiren Becker ,  Anand Haridass ,  Bao Truong

IPC分类号： H03K19/00

CPC分类号： H03K5/00 ,  H03K5/135 ,  H04L25/0276

摘要： Data busses are configured as N differential channels driven by a data signal and its complement through two off-chip drivers (OCDs). Each OCD is preceded by a programmable delay element and a two way MUX. The two data channels either transmit the data signals or a common clock signal as determined by a select signal from a skew controller. The differential signals are received in a differential receiver and a phase detector. The output of the phase detector in each differential channel is routed through an Nx1 MUX. The Nx1 MUX is controlled by the skew controller. The output of the Nx1 MUX is fed back as a phase error feedback signal to the skew controller. Each differential data channel is sequentially selected and the programmable delays are adjusted until the phase error feedback signal from the selected phase detector reaches a predetermined minimum allowable value. Periodic adjustment may be implemented for calibration.

摘要翻译： 数据总线被配置为由数据信号驱动的N个差分信道及其通过两个片外驱动器（OCD）的补码。 每个OCD之前都有可编程延迟元件和双向MUX。 两个数据通道传输数据信号或由偏斜控制器的选择信号确定的公共时钟信号。 差分信号在差分接收机和相位检测器中被接收。 每个差分信道中的相位检测器的输出通过Nx1 MUX进行路由。 Nx1 MUX由偏斜控制器控制。 Nx1 MUX的输出作为相位误差反馈信号反馈到歪斜控制器。 顺序地选择每个差分数据通道，并且调整可编程延迟，直到来自所选相位检测器的相位误差反馈信号达到预定的最小允许值。 可以进行定期调整以进行校准。