公开(公告)号：US20080074998A1

公开(公告)日：2008-03-27

申请号：US11948620

申请日：2007-11-30

申请人： WIREN BECKER ,  Daniel Dreps ,  Frank Ferraiolo ,  Anand Haridass ,  Robert Reese

发明人： WIREN BECKER ,  Daniel Dreps ,  Frank Ferraiolo ,  Anand Haridass ,  Robert Reese

IPC分类号： G01R31/08 ,  G06F11/00

CPC分类号： H01L22/22 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method, apparatus, and computer instructions for managing a set of signal paths for a chip. A defective signal path within the set of signal paths for the chip is detected. Signals are re-routed through the set of signal paths such that the defective signal path is removed from the set of signal paths and sending signals using remaining data signal paths in the set of signal paths and using an extra signal path in response to detecting the defective signal path.

摘要翻译： 一种用于管理用于芯片的一组信号路径的方法，装置和计算机指令。 检测用于芯片的信号路径集合内的有缺陷的信号路径。 信号通过一组信号路径重新路由，使得有缺陷的信号路径从信号路径集合中移除，并使用信号路径组中的剩余数据信号路径发送信号，并且响应于检测到的信号路径 有缺陷的信号路径。

公开(公告)号：US20050007145A1

公开(公告)日：2005-01-13

申请号：US10616845

申请日：2003-07-10

申请人： Daniel Dreps ,  Frank Ferraiolo ,  Anand Haridass ,  Bao Truong

发明人： Daniel Dreps ,  Frank Ferraiolo ,  Anand Haridass ,  Bao Truong

IPC分类号： H03K19/003

CPC分类号： H04L25/0278 ,  H04L25/0296

摘要： A termination network has multiple resistors forming multiple voltage dividers with a common node. Half of the resistors are coupled to the positive power supply voltage with P channel field effect transistors (PFETs) and the other half are coupled to the negative or ground power supply voltage with N channel FETs (NFETs). Logic signals are used to control the gates of the FETs. By modifying which FETs are ON, the termination network can be selectively controlled to produce various offset levels with the same impedance level. The impedance levels may also be modified while maintaining the same offset level. A delay circuit may be selectively employed to feedback control signals after a selected delay time to adjust the threshold level to dynamically or statically optimize signal reception.

公开(公告)号：US20060182215A1

公开(公告)日：2006-08-17

申请号：US11055865

申请日：2005-02-11

申请人： Daniel Dreps ,  Frank Ferraiolo ,  Gary Peterson ,  Robert Reese

发明人： Daniel Dreps ,  Frank Ferraiolo ,  Gary Peterson ,  Robert Reese

IPC分类号： H04L7/00

CPC分类号： H04L7/005 ,  G11C19/287 ,  H03K5/133 ,  H03K2005/00058 ,  H04L7/0338

摘要： A method and apparatus for de-skewing and aligning digital data received over and elastic interface bus is disclosed. Upon receiving the data, it is sent through a programmable delay line. While in the programmable delay line, the data is sampled at three points within the data's eye pattern. The three sampling points are dynamically adjusted to maximize coverage of the data's eye pattern. During the adjustment of the sampling points to optimally cover the data's eye pattern, delayed data is sampled from an alternate sampler to prevent sampling from the functional sampler while the delay in the primary sampler is adjusted. Sampling from the alternate sampler while changing the sampling points of the functional sampler serves to reduce glitches that may occur by sampling the functional sampler while its sampling parameters are changed. The method and apparatus allow for alternate eye tracking and wraparound eye tracking.

摘要翻译： 公开了一种用于使接收到的数字数据进行偏斜和对准的弹性接口总线的方法和装置。 在接收到数据后，通过可编程延迟线发送。 在可编程延迟线中，数据在数据眼图中的三个点进行采样。 动态调整三个采样点，以最大化数据眼图的覆盖范围。 在调整采样点以最佳地覆盖数据的眼图时，延迟数据从备用采样器采样，以防止在主采样器中的延迟调整时从功能采样器采样。 在更换功能采样器的采样点时，从备用采样器进行采样可以减少在采样参数变化时采样功能采样器可能发生的毛刺。 该方法和装置允许替代眼睛跟踪和环绕眼睛跟踪。

公开(公告)号：US20060181320A1

公开(公告)日：2006-08-17

申请号：US11055851

申请日：2005-02-11

申请人： Daniel Dreps ,  Frank Ferraiolo ,  Robert Reese ,  Glen Wiedemeier

发明人： Daniel Dreps ,  Frank Ferraiolo ,  Robert Reese ,  Glen Wiedemeier

IPC分类号： H03L7/06

CPC分类号： H04L7/033 ,  H03L7/0814 ,  H04L7/0008 ,  H04L7/0037 ,  H04L7/0041 ,  H04L25/0272

摘要： Data signals are transmitted over transmission lines in groups to receivers in a receiving IC. Each group of data signals has a differential clock used in synchronizing and detecting the data signals. The data signal eye windows vary with timing jitter in the data signals relative to the clock edges and the asymmetry in a compensated clock signal detected from the differential clock using a duty cycle adjustment circuit. Error detection determines if the clock asymmetry is affecting the eye window of the data signals. Control signals selectively adjust the gain of differential stages generating the compensated clock to modify the duty cycle of the compensated clock. The eye window of the data signals are monitored and used as feedback to servo the control signals to optimize the duty cycle of the compensated clock signal for sampling the data signals.

摘要翻译： 数据信号通过传输线组传送到接收IC中的接收器。 每组数据信号具有用于同步和检测数据信号的差分时钟。 数据信号眼窗随数据信号相对于时钟边缘的定时抖动和使用占空比调整电路从差分时钟检测到的补偿时钟信号的不对称性而变化。 错误检测确定时钟不对称是否影响数据信号的眼睛窗口。 控制信号选择性地调节产生补偿时钟的差分级的增益，以修改补偿时钟的占空比。 数据信号的眼窗被监视并用作伺服控制信号的反馈，以优化用于采样数据信号的经补偿的时钟信号的占空比。

公开(公告)号：US20060181303A1

公开(公告)日：2006-08-17

申请号：US11055805

申请日：2005-02-11

申请人： Daniel Dreps ,  Frank Ferraiolo ,  Robert Reese ,  Glen Wiedemeier

发明人： Daniel Dreps ,  Frank Ferraiolo ,  Robert Reese ,  Glen Wiedemeier

IPC分类号： H03K19/003

CPC分类号： H04L25/0292 ,  G06F13/4072 ,  H04L7/0033 ,  H04L25/0272

摘要： Pseudo-differential drivers and receivers are used to communicate data signals between two or more IC chips. The data paths are aligned using programmable delay circuitry to de-skew each data path. A programmable reference generator is used to generate a reference voltage used by one or a group of receivers to detect the data signals. The reference voltage is adjustable using coarse as well as fine digitally controlled voltage increments. Test signals are sent from the driver to the receiver and the reference voltage is varied over its adjustable range using the coarse and fine adjustment controls while circuitry determines a measure of the detection timing jitter on successive transitions of the test signal. The operational value of the reference voltage is set to the value where the detection timing jitter is determined to be a minimum.

摘要翻译： 伪差分驱动器和接收器用于在两个或更多个IC芯片之间传送数据信号。 使用可编程延迟电路对数据路径进行对齐，以使每个数据路径发生偏移。 可编程参考发生器用于产生一个或一组接收机使用的参考电压，以检测数据信号。 参考电压可以使用粗调以及精细的数字控制电压增量进行调节。 测试信号从驱动器发送到接收器，并且参考电压在其可调节范围内使用粗略和精细调节控制来改变，而电路确定测试信号的连续转换时的检测定时抖动的量度。 将参考电压的操作值设定为检测定时抖动确定为最小的值。

公开(公告)号：US20060184817A1

公开(公告)日：2006-08-17

申请号：US11055866

申请日：2005-02-11

申请人： Daniel Dreps ,  Frank Ferraiolo ,  Gary Peterson ,  Robert Reese

发明人： Daniel Dreps ,  Frank Ferraiolo ,  Gary Peterson ,  Robert Reese

IPC分类号： G06F1/04

CPC分类号： G06F5/06 ,  G06F1/10

摘要： A mechanism for de-skewing and aligning data bits sent between two chips on an elastic interface. On the receiving end of an elastic interface, the eye of each data bit within a clock/data group is delayed by less than a bit time to align the eyes with the nearest clock edge of a received clock signal. In addition to aligning the eyes of the individual data bits with the nearest clock edge, IAP patterns are used to determine the amount of further delay needed to line up the individual data beats from each data bit. If the data beats for the data bits are not aligned, all but the slowest data beat are delayed to align the data beats for all bits. The additional delay is achieved using sample latches that result in a delayed signal with less jitter. As a result of having less jitter, the received, de-skewed, and aligned clock/data group can be forwarded to the operative portion of the receiving chip at an increased frequency.

摘要翻译： 用于在弹性界面上在两个芯片之间发送的数据位的偏斜和对准的机制。 在弹性接口的接收端，时钟/数据组内的每个数据位的眼睛被延迟小于一点时间，以使眼睛与接收到的时钟信号的最近的时钟沿对齐。 除了将各个数据位的眼睛与最近的时钟边沿对齐之外，还使用IAP模式来确定从每个数据位排列各个数据节拍所需的进一步延迟量。 如果数据位的数据跳转不对齐，除了最慢的数据跳转之外，除了所有位的数据跳转之外，都会被延迟。 使用采样锁存器实现额外的延迟，导致延迟信号抖动较小。 由于具有较少的抖动，所接收的，去偏斜的和对准的时钟/数据组可以以增加的频率转发到接收芯片的操作部分。

公开(公告)号：US20060176096A1

公开(公告)日：2006-08-10

申请号：US11056798

申请日：2005-02-10

申请人： Daniel Dreps ,  Frank Ferraiolo ,  Daniel Friedman ,  Seongwon Kim ,  Robert Reese ,  Hector Saenz ,  Michael Sperling

发明人： Daniel Dreps ,  Frank Ferraiolo ,  Daniel Friedman ,  Seongwon Kim ,  Robert Reese ,  Hector Saenz ,  Michael Sperling

IPC分类号： H03H11/26

CPC分类号： H03K5/133 ,  H03K2005/00039 ,  H03K2005/0013

摘要： A power supply voltage insensitive delay element is provided that enables a digital signal to be delayed without variation due to power supply vulnerabilities. Current is limited through the transistors of the delay element using bias voltages produced by a bias voltage generator coupled to the delay element. The bias voltage generator and the delay element are included in a delay line which facilitates the providing of a delay that is insensitive to voltage fluctuations.

摘要翻译： 提供了电源电压不敏感延迟元件，其使数字信号由于电源漏洞而被延迟而没有变化。 使用由耦合到延迟元件的偏置电压发生器产生的偏置电压，延迟元件的晶体管限制电流。 偏置电压发生器和延迟元件包括在延迟线中，这有助于提供对电压波动不敏感的延迟。

公开(公告)号：US20070288679A1

公开(公告)日：2007-12-13

申请号：US11695679

申请日：2007-04-03

申请人： Daniel Dreps ,  Frank Ferraiolo ,  Kevin Gower ,  Roger Rippens

发明人： Daniel Dreps ,  Frank Ferraiolo ,  Kevin Gower ,  Roger Rippens

IPC分类号： G06F13/36 ,  G06F12/00

CPC分类号： G11C5/04

摘要： A dual inline memory module (DIMM) includes a card having a length of about 151.2 to about 151.5 millimeters, a plurality of individual local memory devices attached to the card, and a buffer device attached to the card, the buffer device configured for converting a packetized memory interface. The card includes at least 276 pins configured thereon including a plurality of high-speed bus interface pills arranged on said card for communicating with a plurality of high-speed busses. The high-speed bus interface pins associated with a single high-speed bus are located on one side of the card with respect to a midpoint of the length of the card, thus the pin assignments are defined such that the performance of the DIMM in a system is optimized for high frequency operation.

摘要翻译： 双列直插式存储器模块（DIMM）包括具有大约151.2至大约151.5毫米的长度的卡，连接到卡的多个单独的本地存储器件以及连接到卡的缓冲器装置，缓冲器装置被配置为将 打包内存界面。 该卡包括至少276个引脚，其构造为包括布置在所述卡上的多个高速总线接口卡，用于与多个高速总线通信。 与单个高速总线相关联的高速总线接口引脚相对于卡的长度的中点位于卡的一侧，因此引脚分配被定义为使得DIMM的性能在 系统针对高频操作进行了优化。

公开(公告)号：US20060181324A1

公开(公告)日：2006-08-17

申请号：US11215416

申请日：2005-08-30

申请人： Daniel Dreps ,  Frank Ferraiolo ,  Daniel Friedman ,  Seongwon Kim ,  Hector Saenz ,  Michael Sperling

发明人： Daniel Dreps ,  Frank Ferraiolo ,  Daniel Friedman ,  Seongwon Kim ,  Hector Saenz ,  Michael Sperling

IPC分类号： H03H11/26

CPC分类号： H03H11/265 ,  H03K5/133 ,  H03K2005/00039

摘要： Delay elements and delay lines having glitchless operation are disclosed. By way of example, apparatus for delaying an input signal comprises a reference current generator for generating a constant current, wherein the constant current is insensitive to a variation of a power supply voltage, at least one variable bias voltage generator coupled to the reference current generator for generating a set of bias voltages based on the constant current generated by the reference current generator and a digitally programmable delay control input, and at least one delay element coupled to the at least one variable bias voltage generator for delaying the input signal by a constant delay which is determined by the set of bias voltages generated by the at least one variable bias voltage generator.

摘要翻译： 公开了具有无毛刺操作的延迟元件和延迟线。 作为示例，用于延迟输入信号的装置包括用于产生恒定电流的参考电流发生器，其中恒定电流对电源电压的变化不敏感，耦合到参考电流发生器的至少一个可变偏置电压发生器 用于基于由参考电流发生器和数字可编程延迟控制输入产生的恒定电流产生一组偏置电压，以及耦合到所述至少一个可变偏置电压发生器的至少一个延迟元件，用于将输入信号延迟常数 由所述至少一个可变偏置电压发生器产生的偏置电压组确定的延迟。

公开(公告)号：US20070195572A1

公开(公告)日：2007-08-23

申请号：US11735640

申请日：2007-04-16

申请人： Daniel Dreps ,  Frank Ferraiolo ,  Kevin Gower ,  Mark Kellogg ,  Roger Rippens

发明人： Daniel Dreps ,  Frank Ferraiolo ,  Kevin Gower ,  Mark Kellogg ,  Roger Rippens

IPC分类号： G11C5/06

CPC分类号： G11C5/04

摘要： A dual inline memory module (DIMM) includes a card having a length of about 151.2 to about 151.5 millimeters, a pluality of individual local memory devices attached to the card, and a buffer device attached to the card, the buffer device configured for converting a packetized memory interface. The card includes at least 276 pins configured thereon.

摘要翻译： 双列直插式存储器模块（DIMM）包括具有约151.2至约151.5毫米的长度的卡，连接到该卡的各个本地存储器件的抽头以及附接到该卡的缓冲器装置，缓冲器装置被配置为将 打包内存界面。 该卡片包括至少276个配置在其上的针脚。