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公开(公告)号：US20140033330A1
公开(公告)日：2014-01-30
申请号：US13561185
申请日：2012-07-30
CPC分类号： G06F21/73 , G06F7/588 , G06F21/00 , G06F21/30 , G06F2221/2129 , H02H3/24 , H04L9/3278
摘要： Methods and circuits for undiscoverable physical chip identification are disclosed. Embodiments of the present invention provide an intrinsic bit element that comprises two transistors. The two transistors form a pair in which one transistor has a wide variability in threshold voltage and the other transistor has a narrow variability in threshold voltage. The wide variability is achieved by making a transistor with a smaller width and length than the other transistor in the pair. The variation of the threshold voltage of the wide variability transistor means that in the case of copies of intrinsic bit elements being made, some of the “copied” wide variability transistors will have significantly different threshold voltages, causing some of the intrinsic bit elements of a copied chip to read differently than in the original chip from which they were copied.
摘要翻译： 公开了用于不可发现的物理芯片识别的方法和电路。 本发明的实施例提供了包括两个晶体管的本征位元件。 两个晶体管形成一对，其中一个晶体管具有很大的阈值电压变化，另一个晶体管的阈值电压变化很小。 通过制造具有比该对中的另一个晶体管更小的宽度和长度的晶体管来实现广泛的变化。 宽变化率晶体管的阈值电压的变化意味着在内部位元素复制的情况下，一些“复制的”宽变化性晶体管将具有明显不同的阈值电压，导致一些固有位元素 复制芯片的读取方式与原始芯片的复制方式不同。
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公开(公告)号：US08950008B2
公开(公告)日：2015-02-03
申请号：US13561185
申请日：2012-07-30
CPC分类号： G06F21/73 , G06F7/588 , G06F21/00 , G06F21/30 , G06F2221/2129 , H02H3/24 , H04L9/3278
摘要： Methods and circuits for undiscoverable physical chip identification are disclosed. Embodiments of the present invention provide an intrinsic bit element that comprises two transistors. The two transistors form a pair in which one transistor has a wide variability in threshold voltage and the other transistor has a narrow variability in threshold voltage. The wide variability is achieved by making a transistor with a smaller width and length than the other transistor in the pair. The variation of the threshold voltage of the wide variability transistor means that in the case of copies of intrinsic bit elements being made, some of the “copied” wide variability transistors will have significantly different threshold voltages, causing some of the intrinsic bit elements of a copied chip to read differently than in the original chip from which they were copied.
摘要翻译： 公开了用于不可发现的物理芯片识别的方法和电路。 本发明的实施例提供了包括两个晶体管的本征位元件。 两个晶体管形成一对，其中一个晶体管具有很大的阈值电压变化，另一个晶体管的阈值电压变化很小。 通过制造具有比该对中的另一个晶体管更小的宽度和长度的晶体管来实现广泛的变化。 宽变化率晶体管的阈值电压的变化意味着在内部位元素复制的情况下，一些“复制的”宽变化性晶体管将具有明显不同的阈值电压，导致一些固有位元素 复制芯片的读取方式与原始芯片的复制方式不同。
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3.发明申请PHYSICAL DESIGN SYMMETRY AND INTEGRATED CIRCUITS ENABLING THREE DIMENTIONAL (3D) YIELD OPTIMIZATION FOR WAFER TO WAFER STACKING 有权物理设计对称和集成电路实现三维（3D）的优化用于波形堆叠公开(公告)号：US20130307159A1
公开(公告)日：2013-11-21
申请号：US13471869
申请日：2012-05-15
申请人： John Matthew Safran , Daniel Jacob Fainstein , Gary W. Maier , Yunsheng Song , Norman Whitelaw Robson
发明人： John Matthew Safran , Daniel Jacob Fainstein , Gary W. Maier , Yunsheng Song , Norman Whitelaw Robson
IPC分类号： H01L23/48 , H01L23/488 , H01L23/485 , H01L21/50
CPC分类号： H01L24/94 , H01L23/481 , H01L23/50 , H01L24/06 , H01L24/13 , H01L24/16 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/06181 , H01L2224/13025 , H01L2224/16146 , H01L2224/8113 , H01L2224/81132 , H01L2224/94 , H01L2225/06513 , H01L2225/06541 , H01L2225/06565 , H01L2225/06593 , H01L2224/81
摘要： One of the wafers in a semiconductor wafer to wafer stack can be rotated a predefined number of positions, relative to a previous wafer in the stack, and bonded in the position in which the maximum number of good die are aligned. An adjustment circuit on each die reroutes signals received from a pad that has been relocated due to rotation. A communication channel formed from a pair of pads that are interconnected by a Through Substrate Vias can be placed in each die and can convey selected information from one die to the next. A code representative of the position orientation of each die can be recorded in a Programmable Read Only Memory located on each die, or may be down loaded from a remote source. Any additional wafer may be stacked serially, and each one may be rotated relative to the wafer that precedes it in the stack.
摘要翻译： 半导体晶片到晶片堆叠中的晶片之一可以相对于堆叠中的先前晶片旋转预定数量的位置，并且结合到最佳数量的芯片对准的位置。 每个模具上的调整电路重新路由从由于旋转而被重定位的焊盘接收到的信号。 由通过穿透基板通孔互连的一对焊盘形成的通信通道可以放置在每个管芯中，并且可以将选定的信息从一个管芯传送到下一个管芯。 代表每个管芯的位置取向的代码可以记录在位于每个管芯上的可编程只读存储器中，或者可以从远程源下载。 任何附加的晶片可以串联堆叠，并且每个晶片可以相对于在堆叠中的晶片前面的晶片旋转。
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4.发明授权Physical design symmetry and integrated circuits enabling three dimentional (3D) yield optimization for wafer to wafer stacking 有权物理设计对称性和集成电路，可实现晶圆到晶圆堆叠的三维（3D）屈服优化公开(公告)号：US09029234B2
公开(公告)日：2015-05-12
申请号：US13471869
申请日：2012-05-15
申请人： John Matthew Safran , Daniel Jacob Fainstein , Gary W. Maier , Yunsheng Song , Norman Whitelaw Robson
发明人： John Matthew Safran , Daniel Jacob Fainstein , Gary W. Maier , Yunsheng Song , Norman Whitelaw Robson
CPC分类号： H01L24/94 , H01L23/481 , H01L23/50 , H01L24/06 , H01L24/13 , H01L24/16 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/06181 , H01L2224/13025 , H01L2224/16146 , H01L2224/8113 , H01L2224/81132 , H01L2224/94 , H01L2225/06513 , H01L2225/06541 , H01L2225/06565 , H01L2225/06593 , H01L2224/81
摘要： One of the wafers in a semiconductor wafer to wafer stack can be rotated a predefined number of positions, relative to a previous wafer in the stack, and bonded in the position in which the maximum number of good die are aligned. An adjustment circuit on each die reroutes signals received from a pad that has been relocated due to rotation. A communication channel formed from a pair of pads that are interconnected by a Through Substrate Vias can be placed in each die and can convey selected information from one die to the next. A code representative of the position orientation of each die can be recorded in a Programmable Read Only Memory located on each die, or may be down loaded from a remote source. Any additional wafer may be stacked serially, and each one may be rotated relative to the wafer that precedes it in the stack.
摘要翻译： 半导体晶片到晶片堆叠中的晶片之一可以相对于堆叠中的先前晶片旋转预定数量的位置，并且结合到最佳数量的芯片对准的位置。 每个模具上的调整电路重新路由从由于旋转而被重定位的焊盘接收到的信号。 由通过穿透基板通孔互连的一对焊盘形成的通信通道可以放置在每个管芯中，并且可以将选定的信息从一个管芯传送到下一个管芯。 代表每个管芯的位置取向的代码可以记录在位于每个管芯上的可编程只读存储器中，或者可以从远程源下载。 任何附加的晶片可以串联堆叠，并且每个晶片可以相对于在堆叠中的晶片前面的晶片旋转。
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