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    Low voltage high-speed differential logic devices and method of use thereof
    2.
    发明授权
    Low voltage high-speed differential logic devices and method of use thereof 有权
    低电压高速差分逻辑器件及其使用方法

    公开(公告)号：US07098697B2

    公开(公告)日：2006-08-29

    申请号：US10857238

    申请日：2004-05-28

    申请人： Daniel Kucharski ,  Kevin Kornegay

    发明人： Daniel Kucharski ,  Kevin Kornegay

    IPC分类号： H03K19/086

    CPC分类号： H03K3/2885 ,  H03K17/6264 ,  H03K19/001 ,  H03K19/086 ,  H03K19/212

    摘要： A circuit topology for high speed low voltage logic circuits is disclosed that reduces the number of levels of stacked active circuit elements from 3 to 2. Circuits providing a variety of logic functions are presented, including a latch, an exclusive OR gate, a combination XOR and latch, a multiplexer and a demultiplexer. Circuits built according to the principles of the invention have been operated at speeds of 40 GHz. The circuit topology can operate at supply voltages as low as 2V (for silicon or silicon-germanium based devices) and provide power saving of 25%–50% or more, depending on the logic function. In some embodiments, circuits comprising single ended or differential inputs can be provided.

    摘要翻译： 公开了一种用于高速低电压逻辑电路的电路拓扑，其将堆叠的有源电路元件的电平数量从3减少到2.提供了各种逻辑功能的电路，包括锁存器，异或门，组合XOR 并锁存，复用器和解复用器。 根据本发明的原理构建的电路已经以40GHz的速度运行。 电路拓扑可以在低至2V的电源电压（基于硅或硅锗器件）下工作，并且可根据逻辑功能提供25％-50％以上的功率节省。 在一些实施例中，可以提供包括单端或差分输入的电路。

    Low voltage high-speed differential logic devices and method of use thereof
    4.
    发明申请
    Low voltage high-speed differential logic devices and method of use thereof 有权
    低电压高速差分逻辑器件及其使用方法

    公开(公告)号：US20050264319A1

    公开(公告)日：2005-12-01

    申请号：US10857238

    申请日：2004-05-28

    申请人： Daniel Kucharski ,  Kevin Kornegay

    发明人： Daniel Kucharski ,  Kevin Kornegay

    IPC分类号： H03K3/2885 ,  H03K17/62 ,  H03K19/00 ,  H03K19/0175 ,  H03K19/086 ,  H03K19/20 ,  H03K19/21

    CPC分类号： H03K3/2885 ,  H03K17/6264 ,  H03K19/001 ,  H03K19/086 ,  H03K19/212

    摘要： A circuit topology for high speed low voltage logic circuits is disclosed that reduces the number of levels of stacked active circuit elements from 3 to 2. Circuits providing a variety of logic functions are presented, including a latch, an exclusive OR gate, a combination XOR and latch, a multiplexer and a demultiplexer. Circuits built according to the principles of the invention have been operated at speeds of 40 GHz. The circuit topology can operate at supply voltages as low as 2V (for silicon or silicon-germanium based devices) and provide power saving of 25%-50% or more, depending on the logic function. In some embodiments, circuits comprising single ended or differential inputs can be provided.

    摘要翻译： 公开了一种用于高速低电压逻辑电路的电路拓扑，其将堆叠的有源电路元件的电平数量从3减少到2.提供了各种逻辑功能的电路，包括锁存器，异或门，组合XOR 并锁存，复用器和解复用器。 根据本发明的原理构建的电路已经以40GHz的速度运行。 电路拓扑可以在低至2V的电源电压（基于硅或硅锗器件）下工作，并且可根据逻辑功能提供25％-50％以上的功率节省。 在一些实施例中，可以提供包括单端或差分输入的电路。