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    PIPELINE POWER GATING
    4.
    发明申请
    PIPELINE POWER GATING 有权
    管道功率补偿

    公开(公告)号：US20130009697A1

    公开(公告)日：2013-01-10

    申请号：US13176842

    申请日：2011-07-06

    申请人： Daniel W. Bailey ,  Aaron S. Rogers ,  James J. Montanaro ,  Bradley G. Burgess ,  Peter J. Hannan

    发明人： Daniel W. Bailey ,  Aaron S. Rogers ,  James J. Montanaro ,  Bradley G. Burgess ,  Peter J. Hannan

    IPC分类号： G05F3/02

    CPC分类号： H03K19/0013 ,  H03K19/0016

    摘要： Leakage current is reduced in a plurality of gates coupled between source storage elements and destination storage elements by waking the plurality of gates to allow current flow in response to assertion of any source clock enable signals that enable clocking of the source storage elements. The gates are slept to reduce leakage current in the plurality of gates, in response to assertion of a destination clock enable signal and all of the one or more source clock enable signals being deasserted, the destination clock enable signal enabling clocking of the destination storage elements.

    摘要翻译： 通过唤醒多个门以允许电流流动响应于使得能够对源存储元件进行时钟的任何源时钟使能信号的断言，耦合在源存储元件和目的地存储元件之间的多个栅极中的泄漏电流减小。 响应于确定目的地时钟使能信号并且所有一个或多个源时钟使能信号被断言，门被睡眠以减少多个门中的泄漏电流，目的地时钟使能信号使得能够对目的地存储元件进行时钟 。

    Techniques for integrated circuit clock management
    5.
    发明授权
    Techniques for integrated circuit clock management 有权
    集成电路时钟管理技术

    公开(公告)号：US07737752B2

    公开(公告)日：2010-06-15

    申请号：US11750267

    申请日：2007-05-17

    申请人： Craig Eaton ,  Daniel W. Bailey

    发明人： Craig Eaton ,  Daniel W. Bailey

    IPC分类号： H03K3/00

    CPC分类号： G06F1/08 ,  H03L7/18

    摘要： A clock generator (622) includes a first circuit (812) and a second circuit (814). The first circuit (812) includes a first clock input configured to receive a first clock signal at a first frequency, a second clock input configured to receive a second clock signal at the first frequency, and an output. The second clock signal is out-of-phase with the first clock signal. The second circuit (814) is coupled to the first circuit (812) and includes a mode signal input configured to receive a mode signal. The output of the first circuit (812) is configured to provide a generated clock signal whose effective frequency is based on the first and second clock signals and the mode signal.

    摘要翻译： 时钟发生器（622）包括第一电路（812）和第二电路（814）。 第一电路（812）包括被配置为以第一频率接收第一时钟信号的第一时钟输入，被配置为以第一频率接收第二时钟信号的第二时钟输入和输出。 第二个时钟信号与第一个时钟信号不同相。 第二电路（814）耦合到第一电路（812），并且包括被配置为接收模式信号的模式信号输入。 第一电路（812）的输出被配置为提供其有效频率基于第一和第二时钟信号和模式信号的生成的时钟信号。

    Power monitoring device and methods thereof
    6.
    发明授权
    Power monitoring device and methods thereof 失效
    电力监控装置及其方法

    公开(公告)号：US07567135B2

    公开(公告)日：2009-07-28

    申请号：US11947919

    申请日：2007-11-30

    申请人： Aaron S. Rogers ,  Daniel W. Bailey ,  Roger D. Pannell

    发明人： Aaron S. Rogers ,  Daniel W. Bailey ,  Roger D. Pannell

    IPC分类号： H03B5/08 ,  H03B5/12

    CPC分类号： H03B5/32 ,  H03B2201/0208 ,  H03B2201/0266 ,  H03J2200/10

    摘要： To determine performance degradation at functional module in a normal power state due to a power control device, voltages are applied to oscillators at a power diagnostic module. A first voltage is a supply voltage for the data processing device, and a second voltage is a supply voltage applied at a functional module of the data processing device. Counters are adjusted based on the oscillators to determine the oscillators' respective frequencies. In addition, the power diagnostic module can include a timer to measure the length of time that the functional module is in a low-power state, and an analog to digital converter to measure the voltage applied to the functional module during transitions to and from the low-power state.

    摘要翻译： 为了确定由于功率控制装置在正常功率状态下的功能模块的性能下降，电压被施加到功率诊断模块的振荡器。 第一电压是数据处理装置的电源电压，第二电压是在数据处理装置的功能模块上施加的电源电压。 基于振荡器调整计数器以确定振荡器的相应频率。 此外，功率诊断模块可以包括用于测量功能模块处于低功率状态的时间长度的定时器，以及模数转换器，用于测量在向和/或不同的过渡期间施加到功能模块的电压 低功率状态

    Techniques for integrated circuit clock signal manipulation to facilitate functional and speed test
    7.
    发明授权
    Techniques for integrated circuit clock signal manipulation to facilitate functional and speed test 有权
    集成电路时钟信号操作技术，便于功能和速度测试

    公开(公告)号：US07681099B2

    公开(公告)日：2010-03-16

    申请号：US11750275

    申请日：2007-05-17

    申请人： Atchyuth Gorti ,  Tendy The ,  Daniel W. Bailey ,  Bill K. C. Kwan

    发明人： Atchyuth Gorti ,  Tendy The ,  Daniel W. Bailey ,  Bill K. C. Kwan

    IPC分类号： G01R31/28 ,  G06F11/00

    CPC分类号： G01R31/31727

    摘要： An integrated circuit (1600) includes a debug module (1602) and a clock generator (1610). The debug module (1602) is configured to receive a test pattern and provide a mode signal based on the test pattern. The clock generator (1610) includes a first clock input configured to receive a first clock signal, a second clock input configured to receive a second clock signal, and a mode input configured to receive the mode signal. The first and second clock signals are out of phase and have the same clock frequency. The clock generator (1610) is configured to provide a generated clock signal whose effective frequency is based on the first and second clock signals and the mode signal.

    摘要翻译： 集成电路（1600）包括调试模块（1602）和时钟发生器（1610）。 调试模块（1602）被配置为接收测试模式并且基于测试模式提供模式信号。 时钟发生器（1610）包括被配置为接收第一时钟信号的第一时钟输入，被配置为接收第二时钟信号的第二时钟输入和被配置为接收模式信号的模式输入。 第一和第二时钟信号是相位不同的，具有相同的时钟频率。 时钟发生器（1610）被配置为提供其有效频率基于第一和第二时钟信号和模式信号的生成的时钟信号。

    Level shifter device with write assistance and method thereof
    8.
    发明授权
    Level shifter device with write assistance and method thereof 有权
    具有写帮助的电平移位器及其方法

    公开(公告)号：US07679419B2

    公开(公告)日：2010-03-16

    申请号：US11925025

    申请日：2007-10-26

    申请人： Daniel W. Bailey ,  Robert Kaye ,  Julian Selvaraj

    发明人： Daniel W. Bailey ,  Robert Kaye ,  Julian Selvaraj

    IPC分类号： H03L5/00

    CPC分类号： H03K3/356182 ,  H03K3/356113

    摘要： A first transistor of a level shifter provides conductivity between a reference voltage and a node of the level shifter to hold a state of the level shifter output. When an input signal of the level shifter switches, additional transistors assist in reducing the conductivity of the first transistor. This enhances the ability of the level shifter to change the state of the output in response to the change in the input signal, thereby improving the writeability of the level shifter.

    摘要翻译： 电平移位器的第一晶体管提供参考电压和电平移位器的节点之间的电导率，以保持电平移位器输出的状态。 当电平移位器的输入信号切换时，附加的晶体管有助于降低第一晶体管的导电性。 这增强了电平移位器响应于输入信号的变化而改变输出状态的能力，从而提高了电平转换器的可写性。

    LEVEL SHIFTER DEVICE
    9.
    发明申请
    LEVEL SHIFTER DEVICE 有权
    水平更换装置

    公开(公告)号：US20090108903A1

    公开(公告)日：2009-04-30

    申请号：US11925025

    申请日：2007-10-26

    申请人： Daniel W. Bailey ,  Robert Kaye ,  Julian Selvaraj

    发明人： Daniel W. Bailey ,  Robert Kaye ,  Julian Selvaraj

    IPC分类号： H03L5/00

    CPC分类号： H03K3/356182 ,  H03K3/356113

    摘要： A first transistor of a level shifter provides conductivity between a reference voltage and a node of the level shifter to hold a state of the level shifter output. When an input signal of the level shifter switches, additional transistors assist in reducing the conductivity of the first transistor. This enhances the ability of the level shifter to change the state of the output in response to the change in the input signal, thereby improving the writeability of the level shifter.

    摘要翻译： 电平移位器的第一晶体管提供参考电压和电平移位器的节点之间的电导率，以保持电平移位器输出的状态。 当电平移位器的输入信号切换时，附加的晶体管有助于降低第一晶体管的导电性。 这增强了电平移位器响应于输入信号的变化而改变输出状态的能力，从而提高了电平转换器的可写性。

    Techniques for integrated circuit clock management
    10.
    发明申请
    Techniques for integrated circuit clock management 有权
    集成电路时钟管理技术

    公开(公告)号：US20080284474A1

    公开(公告)日：2008-11-20

    申请号：US11750267

    申请日：2007-05-17

    申请人： Craig Eaton ,  Daniel W. Bailey

    发明人： Craig Eaton ,  Daniel W. Bailey

    IPC分类号： H03L7/06

    CPC分类号： G06F1/08 ,  H03L7/18

    摘要： A clock generator (622) includes a first circuit (812) and a second circuit (814). The first circuit (812) includes a first clock input configured to receive a first clock signal at a first frequency, a second clock input configured to receive a second clock signal at the first frequency, and an output. The second clock signal is out-of-phase with the first clock signal. The second circuit (814) is coupled to the first circuit (812) and includes a mode signal input configured to receive a mode signal. The output of the first circuit (812) is configured to provide a generated clock signal whose effective frequency is based on the first and second clock signals and the mode signal.

    摘要翻译： 时钟发生器（622）包括第一电路（812）和第二电路（814）。 第一电路（812）包括被配置为以第一频率接收第一时钟信号的第一时钟输入，被配置为以第一频率接收第二时钟信号的第二时钟输入和输出。 第二个时钟信号与第一个时钟信号不同相。 第二电路（814）耦合到第一电路（812），并且包括被配置为接收模式信号的模式信号输入。 第一电路（812）的输出被配置为提供其有效频率基于第一和第二时钟信号和模式信号的生成的时钟信号。