摘要:
A wordline driver circuit can include single stage level shifters to translate a low voltage level (VGND to Vcc) to a high voltage level (Vnwl to Vpp). A wordline driver can further include a two-stage discharge circuit to pull down a wordline from a boosted high voltage Vpp to a boosted low voltage Vnwl. A two-stage discharge circuit can include (i) a first discharge path that can pull the wordline toward a first low voltage VGND; and (ii) a second discharge path that can pull the wordline toward a lower boosted low voltage Vnwl. Initially discharging a wordline to a first low voltage can reduce the amount of charge injected into a boosted low voltage Vnwl supply. A two-stage discharge circuit can be self timed or externally timed.
摘要:
A semiconductor device memory device (300) can include a sense amplifier (302) enabled according to a first sense signal (setn) and a second sense signal (setp). In a sense operation, a first sense signal (setn) can be driven to a first, below ground potential. Subsequently, in the same sense operation, the first sense signal (setn) can be raised and maintained at a ground potential. Such an approach can substantially eliminate a sense amplifier stall condition that can occur under low temperature and/or low voltage operation. According to another aspect of the embodiments, a more negative logical “0” value can be written back into the memory cell during an access and/or refresh operation. This more negative value is available due to the below ground level provided during a sense operation.
摘要:
In one arrangement, a semiconductor memory device can include a sense amplifier circuit (300) having drive high transistors (P30/P31), drive low transistors (N31/N32) and equalization transistors (N33-N35). Such transistors can have a body bias (VbiasN, VbiasP) that varies according to the operation conditions of the semiconductor memory device. Such variations can include any of: manufacturing process variations, operating temperature, or operating voltage.
摘要翻译:在一种布置中,半导体存储器件可以包括具有驱动高晶体管(P 30 / P 31),驱动低晶体管(N 31 / N 32)和均衡晶体管(N 33 -N 35)的读出放大器电路(300)。 这种晶体管可以具有根据半导体存储器件的操作条件而变化的体偏置(VbiasN,VbiasP)。 这种变化可以包括以下任何一种:制造工艺变化,工作温度或工作电压。
摘要:
A defect current contribution elimination technique may be suitable for dynamic random access memories (DRAMs) and other memory devices. A defect current can be eliminated by using an isolation circuit (106) between bitlines (102-0 and 102-1) and an associated sense amplifier circuit (104). Isolation circuit (106) can be controlled by programmable elements, such as fusible links, which are blown at wafer test to isolate the defective bitlines from the sense amplifier circuit. Isolated, defective bitlines may initially float, but based upon the type of defect, such bitlines can be resistively tied to another element, and as a result no DC current will flow. According to another implementation, controllable devices are placed between wordlines (206) and the wordline driver circuits (226-y). A current path through a defective wordline can be similarly cut-off.
摘要:
The invention provides compounds of formula (I): wherein R1 and R2 are as defined in the specification; processes for their preparation; pharmaceutical compositions containing them; a process for preparing the pharmaceutical compositions; and their use in therapy. The compounds are useful as MMP inhibitors.
摘要:
The technology disclosed relates to granular analysis of design data used to prepare chip designs for manufacturing and to identification of similarities and differences among parts of design data files. In particular, it relates to parsing data and organizing into canonical forms, digesting the canonical forms, and comparing digests of design data from different sources, such as designs and libraries of design templates. Organizing the design data into canonical forms generally reduces the sensitivity of data analysis to variations in data that have no functional impact on the design. The details of the granular analysis vary among design languages used to represent aspects of a design. For various design languages, granular analysis includes partitioning design files by header/cell portions, by separate handling of comments, by functionally significant/non-significant data, by whitespace/non-whitespace, and by layer within a unit of design data. The similarities and differences of interest depend on the purpose of the granular analysis. The comparisons are useful in many ways.
摘要:
Explicit representation of molecular shape of molecules is combined with neural network learning methods to provide models with high predictive ability that generalize to different chemical classes where structurally diverse molecules exhibiting similar surface characteristics are treated as similar. A new machine-learning methodology is disclosed that can accept multiple representations of objects and construct models that predict characteristics of those objects. An extension of this methodology can be applied in cases where the representations of the objects are determined by a set of adjustable parameters. An iterative process applies intermediate models to generate new representations of the objects by adjusting said parameters and repeatedly. retrains the models to obtain better predictive models. This method can be applied to molecules because each molecule can have many orientations and conformations (representations) that are determined by a set of translation, rotation and torsion angle parameters.
摘要:
Explicit representation of molecular shape of molecules is combined with neural network learning methods to provide models with high predictive ability that generalize to different chemical classes where structurally diverse molecules exhibiting similar surface characteristics are treated as similar. A new machine-learning methodology that can accept multiple representations of objects and construct models that predict characteristics of those objects. An extension of this methodology can be applied in cases where the representations of the objects are determined by a set of adjustable parameters. An iterative process applies intermediate models to generate new representations of the objects by adjusting said parameters and repeatedly retrains the models to obtain better predictive models. This method can be applied to molecules because each molecule can have many orientations and conformations (representations) that are determined by a set of translation, rotation and torsion angle parameters.
摘要:
A computer driven device for making silk screens suitable for making signs, PC boards, mask, metal, textile graphics and the like is disclosed. The device uses a laser beam to burn holes in a thin sheet of plastic, preferably nylon. The laser beam is directed toward the surface of the nylon screen and the beam is moved incrementally under computer control to position the two before activation of the laser. The desired sign or pattern to be burned into the screen is constructed by means of a microprocessor or PC using a desk top type publishing program. The finished nylon "silk" screen can be used in the same manner as conventional silk screens.
摘要:
A parallel processing circuit is disclosed for use as the processor/memory in a highly parallel processor. The circuit comprises an instruction decoder that generates tables of outputs in response to instructions received at the decoder and a plurality of processor/memories each of which comprises a read/write memory and a processor for producing an output depending at least in part on data read from the memory and instruction information received at the instruction decoder. In addition, the circuit provides means for simultaneously addressing at least one cell in each read/write memory to write data thereto or read data therefrom and means for providing to each processor an output table from the decoder, the particular output table depending on instruction information received at the decoder. Further the processing circuit comprises means for selecting from the output table a particular output depending on data input to the processor. Advantageously, each processor/memory also comprises a flag controller for controlling the reading of a plurality of flags and means for simultaneously addressing each flag controller to read a flag for input into the processor associated therewith.Preferably, each processor is a bit-serial processor with three inputs, two from the read/write memory and one from the flag controller, and two outputs, one to the read/write memory and one to the flag controller; and the decoder and the plurality of processor/memories and formed on a single, integrated circuit chip.