公开(公告)号：US06376308B1

公开(公告)日：2002-04-23

申请号：US09487073

申请日：2000-01-19

申请人： Fei Wang ,  David K. Foote ,  Bharath Rangarajan ,  George Kluth

发明人： Fei Wang ,  David K. Foote ,  Bharath Rangarajan ,  George Kluth

IPC分类号： H01L218247

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A process for fabricating an EEPROM device having pocket substrate regions includes forming a pattern composite layer overlying a principal surface of a semiconductor substrate. The pattern composite layer includes a dielectric layer and a resist layer overlying the dielectric layer. Processing is carried out to reduce the lateral dimension of the resist layer relative to the dielectric layer thereby exposing an upper surface of the dielectric layer. A doping process is carried out in which dopants penetrate the exposed upper surface of the dielectric layer and enter the semiconductor substrate immediately below the exposed upper surface of the dielectric layer. Upon conforming the pocket regions, an oxidation process is carried out to form bit-line oxide regions in the semiconductor substrate.

摘要翻译： 一种用于制造具有袋基底区域的EEPROM器件的工艺包括形成覆盖在半导体衬底的主表面上的图案复合层。 图案复合层包括介电层和覆盖电介质层的抗蚀剂层。 进行处理以减小抗蚀剂层相对于电介质层的横向尺寸，从而暴露电介质层的上表面。 进行掺杂工艺，其中掺杂剂穿透介电层的暴露的上表面并进入电介质层暴露的上表面正下方的半导体衬底。 在使袋区域一致时，进行氧化处理以在半导体衬底中形成位线氧化物区域。

公开(公告)号：US06168993A

公开(公告)日：2001-01-02

申请号：US09487922

申请日：2000-01-19

申请人： David K. Foote ,  Bharath Rangarajan ,  George Kluth ,  Fei Wang

发明人： David K. Foote ,  Bharath Rangarajan ,  George Kluth ,  Fei Wang

IPC分类号： H01L218247

CPC分类号： H01L29/66825

摘要： A process for fabricating a semiconductor device includes the step of processing a patterned resist layer to vary the lateral dimensions of the patterned resist layer while forming doped regions in a semiconductor substrate. A graded junction profile is formed by creating a patterned resist layer having a first substantially vertical edge surface. A doping process is carried out to form a first doped region in the semiconductor substrate having a junction profile substantially continuous with the first substantially vertical edge surface. The patterned resist layer is processed to form a second substantially vertical edge surface, which is laterally displaced from the first substantially vertical edge surface. A doping process is carried out to form a second doped region having a junction profile that is substantially continuous with the second substantially vertical edge surface. The junction profiles of the first and second doped regions form a graded junction within the semiconductor substrate. The process can be repeated to form a wide variety of graded junction profiles within a semiconductor substrate.

摘要翻译： 制造半导体器件的方法包括处理图案化的抗蚀剂层以改变图案化的抗蚀剂层的横向尺寸同时在半导体衬底中形成掺杂区域的步骤。 通过产生具有第一基本上垂直的边缘表面的图案化抗蚀剂层来形成分级结型材。 执行掺杂工艺以在半导体衬底中形成具有与第一基本上垂直的边缘表面基本连续的接合轮廓的第一掺杂区域。 图案化的抗蚀剂层被加工成形成第二基本上垂直的边缘表面，其从第一基本上垂直的边缘表面横向移位。 进行掺杂工艺以形成具有与第二基本上垂直的边缘表面基本连续的接合轮廓的第二掺杂区域。 第一和第二掺杂区的结型材在半导体衬底内形成渐变结。 可以重复该过程以在半导体衬底内形成多种渐变连接轮廓。

公开(公告)号：US06436766B1

公开(公告)日：2002-08-20

申请号：US09430493

申请日：1999-10-29

申请人： Bharath Rangarajan ,  David K. Foote ,  Fei Wang ,  Dawn M. Hopper ,  Stephen K. Park ,  Jack Thomas ,  Mark Chang ,  Mark Ramsbey

发明人： Bharath Rangarajan ,  David K. Foote ,  Fei Wang ,  Dawn M. Hopper ,  Stephen K. Park ,  Jack Thomas ,  Mark Chang ,  Mark Ramsbey

IPC分类号： H01L218247

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A process for fabricating a memory cell in a two-bit EEPROM device including forming an ONO layer overlying a semiconductor substrate, depositing a hard mask overlying the ONO layer, and patterning the hard mask. The hard mask is preferably made from polysilicon or silicon. The process further includes doping the semiconductor substrate with boron causing p-type regions to form in the semiconductor substrate, and doping the semiconductor substrate with n-type dopants, such as arsenic, causing n-type regions to form in the semiconductor substrate. The exposed ONO layer is then etched to expose part of the semiconductor substrate, and a bit-line oxide region is formed overlying the semiconductor substrate. The hard mask is then removed, preferably using a plasma etch process.

摘要翻译： 一种用于在二位EEPROM器件中制造存储单元的方法，包括形成覆盖在半导体衬底上的ONO层，沉积覆盖在ONO层上的硬掩模，以及对该硬掩模进行构图。 硬掩模优选由多晶硅或硅制成。 该工艺还包括用硼掺杂导致在半导体衬底中形成p型区域的半导体衬底，并且用诸如砷的n型掺杂剂掺杂半导体衬底，从而在半导体衬底中形成n型区域。 然后对暴露的ONO层进行蚀刻以暴露半导体衬底的一部分，并且在半导体衬底上形成位线氧化物区域。 然后去除硬掩模，优选使用等离子体蚀刻工艺。

公开(公告)号：US06242305B1

公开(公告)日：2001-06-05

申请号：US09427404

申请日：1999-10-25

申请人： David K. Foote ,  Hideki Komori ,  Bharath Rangarajan ,  Fei Wang

发明人： David K. Foote ,  Hideki Komori ,  Bharath Rangarajan ,  Fei Wang

IPC分类号： H01L218247

CPC分类号： H01L27/11568 ,  H01L27/115

摘要： A process for fabricating a MONOS device having a buried bit-line includes providing a semiconductor substrate and forming an ONO structure overlying the semiconductor substrate. Thereafter, a hard mask layer is formed to overlie ONO structure, the hard mask layer having an upper surface. To form a trench for the buried bit-line, an etch process is performed on the ONO structure. Thereafter, silicon dioxide is deposited to fill the trench. To control a thickness of the deposited silicon dioxide, a chemical-mechanical-polishing process is performed to planarize the silicon dioxide and form a planar surface continuous with the upper surface of the hard mask layer. Finally, the hard mask layer is removed and the remaining silicon dioxide forms a uniform bit-line oxide layer.

摘要翻译： 制造具有掩埋位线的MONOS器件的工艺包括提供半导体衬底并形成覆盖半导体衬底的ONO结构。 此后，形成硬掩模层以覆盖ONO结构，硬掩模层具有上表面。 为了形成掩埋位线的沟槽，对ONO结构进行蚀刻处理。 此后，沉积二氧化硅以填充沟槽。 为了控制沉积的二氧化硅的厚度，进行化学机械抛光工艺以使二氧化硅平坦化并形成与硬掩模层的上表面连续的平面。 最后，去除硬掩模层，剩余的二氧化硅形成均匀的位线氧化物层。

公开(公告)号：US06528390B2

公开(公告)日：2003-03-04

申请号：US09798667

申请日：2001-03-02

申请人： Hideki Komori ,  David K. Foote ,  Fei Wang ,  Bharath Rangarajan

发明人： Hideki Komori ,  David K. Foote ,  Fei Wang ,  Bharath Rangarajan

IPC分类号： H01L2176

CPC分类号： H01L21/76213

摘要： A method for fabricating a semiconductor structure includes growing regions of oxide on a first structure, to form bit-line regions; wherein said semiconductor structure includes a semiconducting substrate, a patterned ONO layer on said substrate, wherein said patterned ONO layer comprises regions of ONO and exposed regions of said semiconducting substrate, a patterned hard mask layer on said regions of ONO, and a patterned photoresist layer on said patterned hard mask layer.

公开(公告)号：US06297143B1

公开(公告)日：2001-10-02

申请号：US09426743

申请日：1999-10-25

申请人： David K. Foote ,  Bharath Rangarajan ,  Fei Wang ,  Steven K. Park

发明人： David K. Foote ,  Bharath Rangarajan ,  Fei Wang ,  Steven K. Park

IPC分类号： H01L214763

CPC分类号： H01L27/11568 ,  H01L27/11517

摘要： A process for fabricating a MONOS device having a buried bit-line includes providing a semiconductor substrate and forming a mask layer overlying the semiconductor substrate. Thereafter, an etch process is performed to form a trench in the semiconductor substrate. Next, the mask layer is removed and the trench in the semiconductor substrate is filled with a silicon oxide layer. To form a bit-line oxide layer, a planarization process is utilized to planarize the silicon oxide layer and form a planar surface continuous with an upper surface of the semiconductor substrate.

摘要翻译： 用于制造具有掩埋位线的MONOS器件的工艺包括提供半导体衬底并形成覆盖半导体衬底的掩模层。 此后，进行蚀刻处理以在半导体衬底中形成沟槽。 接下来，去除掩模层，并且用氧化硅层填充半导体衬底中的沟槽。 为了形成位线氧化层，利用平面化工艺来平坦化氧化硅层并形成与半导体衬底的上表面连续的平面。

公开(公告)号：US06486029B1

公开(公告)日：2002-11-26

申请号：US09627563

申请日：2000-07-28

申请人： David K. Foote ,  Bharath Rangarajan ,  Stephan K. Park ,  Fei Wang ,  Dawn M. Hopper ,  Jack Thomas ,  Mark Chang ,  Mark Ramsbey

发明人： David K. Foote ,  Bharath Rangarajan ,  Stephan K. Park ,  Fei Wang ,  Dawn M. Hopper ,  Jack Thomas ,  Mark Chang ,  Mark Ramsbey

IPC分类号： H01L218247

CPC分类号： H01L27/11568 ,  H01L27/115 ,  Y10S438/954

摘要： A process for fabricating a memory cell in a two-bit EEPROM device, the process includes forming an ONO layer overlying a semiconductor substrate, depositing a hard mask overlying the ONO layer, and patterning the hard mask. Preferably, the hard mask includes a material selected from the group consisting of tungsten, titanium, titanium nitride, polysilicon, silicon, silicon nitride, silicon oxi-nitride, and silicon rich nitride. In one preferred embodiment, the process further includes implanting the semiconductor substrate with a p-type dopant at an angle substantially normal to the principal surface of the semiconductor substrate and annealing the semiconductor substrate upon implanting the semiconductor substrate with a p-type dopant. In one preferred embodiment, the process further includes implanting the semiconductor substrate with an n-type dopant.

摘要翻译： 一种用于在2位EEPROM器件中制造存储单元的工艺，该工艺包括形成覆盖半导体衬底的ONO层，沉积覆盖在ONO层上的硬掩模，以及对该硬掩模进行构图。 优选地，硬掩模包括选自钨，钛，氮化钛，多晶硅，硅，氮化硅，氧化氮化硅和富氮的氮化物的材料。 在一个优选实施例中，该方法还包括以基本上垂直于半导体衬底的主表面的角度注入具有p型掺杂剂的半导体衬底，并在用p型掺杂剂注入半导体衬底时退火半导体衬底。 在一个优选实施例中，该工艺还包括用n型掺杂剂注入半导体衬底。

公开(公告)号：US06399446B1

公开(公告)日：2002-06-04

申请号：US09429722

申请日：1999-10-29

申请人： Bharath Rangarajan ,  David K. Foote ,  Fei Wang ,  Dawn M. Hopper ,  Stephen K. Park ,  Jack Thomas ,  Mark Chang ,  Mark Ramsbey

发明人： Bharath Rangarajan ,  David K. Foote ,  Fei Wang ,  Dawn M. Hopper ,  Stephen K. Park ,  Jack Thomas ,  Mark Chang ,  Mark Ramsbey

IPC分类号： H01L218247

CPC分类号： H01L27/11568 ,  H01L27/115 ,  Y10S438/945

摘要： A process for fabricating a memory cell in a two-bit EEPROM device including forming an ONO layer overlying a semiconductor substrate, depositing a hard mask overlying the ONO layer, and patterning the hard mask. The hard mask is made from tungsten, titanium, or titanium nitride. The process further includes doping the semiconductor substrate with boron causing p-type regions to form in the semiconductor substrate, and doping the semiconductor substrate with n-type dopants, such as arsenic, causing n-type regions to form in the semiconductor substrate. The exposed ONO layer is then etched to expose part of the semiconductor substrate, and a bit-line oxide region is formed overlying the semiconductor substrate. The hard mask is then stripped, preferably using an H2O2 solution.

摘要翻译： 一种用于在二位EEPROM器件中制造存储单元的方法，包括形成覆盖在半导体衬底上的ONO层，沉积覆盖在ONO层上的硬掩模，以及对该硬掩模进行构图。 硬掩模由钨，钛或氮化钛制成。 该工艺还包括用硼掺杂导致在半导体衬底中形成p型区域的半导体衬底，并且用诸如砷的n型掺杂剂掺杂半导体衬底，从而在半导体衬底中形成n型区域。 然后对暴露的ONO层进行蚀刻以暴露半导体衬底的一部分，并且在半导体衬底上形成位线氧化物区域。 然后将硬掩模剥离，优选使用H 2 O 2溶液。

公开(公告)号：US06207502B1

公开(公告)日：2001-03-27

申请号：US09426255

申请日：1999-10-25

申请人： Kenneth Au ,  David K. Foote ,  Steven K. Park ,  Fei Wang ,  Bharath Rangarajan

发明人： Kenneth Au ,  David K. Foote ,  Steven K. Park ,  Fei Wang ,  Bharath Rangarajan

IPC分类号： H01L218247

CPC分类号： H01L27/11568

摘要： A process for fabricating a MONOS type Flash cell device having a periphery field oxide region and a bit-line region includes providing a semiconductor substrate and growing a barrier silicon oxide layer to overlie semiconductor substrate. Thereafter, a thick silicon nitride layer is formed to overlie the barrier silicon oxide layer. A mask and etch are performed at the periphery of the MONOS type cell to form a trench in the semiconductor substrate. The periphery field oxide region is formed by depositing silicon oxide to fill the trench. Thereafter, a mask and etch are performed at the core of the MONOS cell to form a trench in the semiconductor substrate. The bit-line oxide region is formed by depositing silicon oxide to fill the trench. Thereafter, the thick silicon nitride layer is removed. Since the periphery field oxide region and bit-line region are formed before the thick nitride layer is removed, the formation of an unwanted bird's beak is reduced.

摘要翻译： 一种制造具有外围场氧化物区域和位线区域的MONOS型闪存单元器件的工艺包括：提供半导体衬底并生长覆盖半导体衬底的势垒氧化硅层。 此后，形成厚的氮化硅层以覆盖阻挡氧化硅层。 在MONOS型电池的外围进行掩模和蚀刻，以在半导体衬底中形成沟槽。 通过沉积氧化硅以填充沟槽而形成外围场氧化物区域。 此后，在MONOS单元的核心处进行掩模和蚀刻，以在半导体衬底中形成沟槽。 位线氧化物区域通过沉积氧化硅以填充沟槽而形成。 此后，去除厚的氮化硅层。 由于在去除厚氮化物层之前形成外围场氧化物区域和位线区域，所以不希望的鸟喙形成减少。

公开(公告)号：US06362052B1

公开(公告)日：2002-03-26

申请号：US09627567

申请日：2000-07-28

申请人： Bharath Rangarajan ,  Fei Wang ,  George Kluth ,  Ursula Q. Quinto

发明人： Bharath Rangarajan ,  Fei Wang ,  George Kluth ,  Ursula Q. Quinto

IPC分类号： H01L21336

CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L29/66833

摘要： A process for fabricating a memory cell, the process includes forming an ONO layer overlying a semiconductor substrate, depositing a resist mask overlying the ONO layer, patterning the resist mask, implanting the semiconductor substrate with an n-type dopant, wherein the resist mask is used as an ion implant mask, and etching the resist mask upon implanting the semiconductor substrate with an n-type dopant. In one preferred embodiment, the etching of the resist mask includes performing a blanket anisotropic etch to reduce the thickness of the resist mask and round the edges of the resist mask. Preferably, the blanket anisotropic etch is performed using an etch including an element selected from the group consisting of nitrogen, hydrogen, chlorine, and helium.

摘要翻译： 一种制造存储单元的方法，该方法包括形成覆盖半导体衬底的ONO层，沉积覆盖ONO层的抗蚀剂掩模，图案化抗蚀剂掩模，用n型掺杂剂注入半导体衬底，其中抗蚀剂掩模是 用作离子注入掩模，并且在用n型掺杂剂注入半导体衬底时蚀刻抗蚀剂掩模。 在一个优选实施例中，抗蚀剂掩模的蚀刻包括进行覆盖各向异性蚀刻以减小抗蚀剂掩模的厚度并且围绕抗蚀剂掩模的边缘。 优选地，使用包括选自氮，氢，氯和氦的元素的蚀刻来进行覆盖层各向异性蚀刻。