公开(公告)号：US06436766B1

公开(公告)日：2002-08-20

申请号：US09430493

申请日：1999-10-29

申请人： Bharath Rangarajan ,  David K. Foote ,  Fei Wang ,  Dawn M. Hopper ,  Stephen K. Park ,  Jack Thomas ,  Mark Chang ,  Mark Ramsbey

发明人： Bharath Rangarajan ,  David K. Foote ,  Fei Wang ,  Dawn M. Hopper ,  Stephen K. Park ,  Jack Thomas ,  Mark Chang ,  Mark Ramsbey

IPC分类号： H01L218247

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A process for fabricating a memory cell in a two-bit EEPROM device including forming an ONO layer overlying a semiconductor substrate, depositing a hard mask overlying the ONO layer, and patterning the hard mask. The hard mask is preferably made from polysilicon or silicon. The process further includes doping the semiconductor substrate with boron causing p-type regions to form in the semiconductor substrate, and doping the semiconductor substrate with n-type dopants, such as arsenic, causing n-type regions to form in the semiconductor substrate. The exposed ONO layer is then etched to expose part of the semiconductor substrate, and a bit-line oxide region is formed overlying the semiconductor substrate. The hard mask is then removed, preferably using a plasma etch process.

摘要翻译： 一种用于在二位EEPROM器件中制造存储单元的方法，包括形成覆盖在半导体衬底上的ONO层，沉积覆盖在ONO层上的硬掩模，以及对该硬掩模进行构图。 硬掩模优选由多晶硅或硅制成。 该工艺还包括用硼掺杂导致在半导体衬底中形成p型区域的半导体衬底，并且用诸如砷的n型掺杂剂掺杂半导体衬底，从而在半导体衬底中形成n型区域。 然后对暴露的ONO层进行蚀刻以暴露半导体衬底的一部分，并且在半导体衬底上形成位线氧化物区域。 然后去除硬掩模，优选使用等离子体蚀刻工艺。

公开(公告)号：US06399446B1

公开(公告)日：2002-06-04

申请号：US09429722

申请日：1999-10-29

申请人： Bharath Rangarajan ,  David K. Foote ,  Fei Wang ,  Dawn M. Hopper ,  Stephen K. Park ,  Jack Thomas ,  Mark Chang ,  Mark Ramsbey

发明人： Bharath Rangarajan ,  David K. Foote ,  Fei Wang ,  Dawn M. Hopper ,  Stephen K. Park ,  Jack Thomas ,  Mark Chang ,  Mark Ramsbey

IPC分类号： H01L218247

CPC分类号： H01L27/11568 ,  H01L27/115 ,  Y10S438/945

摘要： A process for fabricating a memory cell in a two-bit EEPROM device including forming an ONO layer overlying a semiconductor substrate, depositing a hard mask overlying the ONO layer, and patterning the hard mask. The hard mask is made from tungsten, titanium, or titanium nitride. The process further includes doping the semiconductor substrate with boron causing p-type regions to form in the semiconductor substrate, and doping the semiconductor substrate with n-type dopants, such as arsenic, causing n-type regions to form in the semiconductor substrate. The exposed ONO layer is then etched to expose part of the semiconductor substrate, and a bit-line oxide region is formed overlying the semiconductor substrate. The hard mask is then stripped, preferably using an H2O2 solution.

摘要翻译： 一种用于在二位EEPROM器件中制造存储单元的方法，包括形成覆盖在半导体衬底上的ONO层，沉积覆盖在ONO层上的硬掩模，以及对该硬掩模进行构图。 硬掩模由钨，钛或氮化钛制成。 该工艺还包括用硼掺杂导致在半导体衬底中形成p型区域的半导体衬底，并且用诸如砷的n型掺杂剂掺杂半导体衬底，从而在半导体衬底中形成n型区域。 然后对暴露的ONO层进行蚀刻以暴露半导体衬底的一部分，并且在半导体衬底上形成位线氧化物区域。 然后将硬掩模剥离，优选使用H 2 O 2溶液。

公开(公告)号：US06486029B1

公开(公告)日：2002-11-26

申请号：US09627563

申请日：2000-07-28

申请人： David K. Foote ,  Bharath Rangarajan ,  Stephan K. Park ,  Fei Wang ,  Dawn M. Hopper ,  Jack Thomas ,  Mark Chang ,  Mark Ramsbey

发明人： David K. Foote ,  Bharath Rangarajan ,  Stephan K. Park ,  Fei Wang ,  Dawn M. Hopper ,  Jack Thomas ,  Mark Chang ,  Mark Ramsbey

IPC分类号： H01L218247

CPC分类号： H01L27/11568 ,  H01L27/115 ,  Y10S438/954

摘要： A process for fabricating a memory cell in a two-bit EEPROM device, the process includes forming an ONO layer overlying a semiconductor substrate, depositing a hard mask overlying the ONO layer, and patterning the hard mask. Preferably, the hard mask includes a material selected from the group consisting of tungsten, titanium, titanium nitride, polysilicon, silicon, silicon nitride, silicon oxi-nitride, and silicon rich nitride. In one preferred embodiment, the process further includes implanting the semiconductor substrate with a p-type dopant at an angle substantially normal to the principal surface of the semiconductor substrate and annealing the semiconductor substrate upon implanting the semiconductor substrate with a p-type dopant. In one preferred embodiment, the process further includes implanting the semiconductor substrate with an n-type dopant.

摘要翻译： 一种用于在2位EEPROM器件中制造存储单元的工艺，该工艺包括形成覆盖半导体衬底的ONO层，沉积覆盖在ONO层上的硬掩模，以及对该硬掩模进行构图。 优选地，硬掩模包括选自钨，钛，氮化钛，多晶硅，硅，氮化硅，氧化氮化硅和富氮的氮化物的材料。 在一个优选实施例中，该方法还包括以基本上垂直于半导体衬底的主表面的角度注入具有p型掺杂剂的半导体衬底，并在用p型掺杂剂注入半导体衬底时退火半导体衬底。 在一个优选实施例中，该工艺还包括用n型掺杂剂注入半导体衬底。

公开(公告)号：US06406960B1

公开(公告)日：2002-06-18

申请号：US09433041

申请日：1999-10-25

申请人： Dawn M. Hopper ,  David K. Foote ,  Bharath Rangarajan ,  Arvind Halliyal

发明人： Dawn M. Hopper ,  David K. Foote ,  Bharath Rangarajan ,  Arvind Halliyal

IPC分类号： H01L218247

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42332 ,  Y10S438/954

摘要： A process for fabricating an ONO layer in a non-volatile memory device including the steps of forming a first silicon oxide layer, a silicon-rich silicon nitride layer and a second silicon oxide layer. The silicon-rich silicon nitride layer is formed by either a PECVD process, an LPCVD, or an RTCVD process. The silicon-rich silicon nitride layer effectively holds electrical charge making the ONO layer particularly useful as a floating gate electrode in a two-bit EEPROM device.

摘要翻译： 一种用于在非易失性存储器件中制造ONO层的工艺，包括形成第一氧化硅层，富硅氮化硅层和第二氧化硅层的步骤。 富硅氮化硅层通过PECVD工艺，LPCVD或RTCVD工艺形成。 富含硅的氮化硅层有效地保持电荷，使得ONO层在二位EEPROM器件中作为浮栅电极特别有用。

公开(公告)号：US06458677B1

公开(公告)日：2002-10-01

申请号：US09433186

申请日：1999-10-25

申请人： Dawn M. Hopper ,  David K. Foote ,  Bharath Rangarajan

发明人： Dawn M. Hopper ,  David K. Foote ,  Bharath Rangarajan

IPC分类号： H01L213205

CPC分类号： H01L21/28282 ,  H01L21/3144 ,  H01L29/7923 ,  Y10S438/954

摘要： A process for fabricating an ONO floating-gate electrode in a two-bit EEPROM device includes the sequential formation of a first silicon oxide layer, a silicon nitride layer and a second silicon oxide layer using an in-situ deposition process in which the silicon nitride layer is not exposed to ambient atmosphere prior to the formation of the top oxide layer. To avoid exposure to ambient atmosphere, the first silicon oxide layer, the silicon nitride layer and the second silicon oxide layer are sequentially formed using either a PECVD or a SACVD process.

摘要翻译： 在2位EEPROM器件中制造ONO浮栅电极的工艺包括使用原位沉积工艺顺序形成第一氧化硅层，氮化硅层和第二氧化硅层，其中氮化硅 层在形成顶部氧化物层之前不暴露于环境大气中。 为了避免暴露于环境大气中，使用PECVD或SACVD工艺顺序地形成第一氧化硅层，氮化硅层和第二氧化硅层。

公开(公告)号：US06395644B1

公开(公告)日：2002-05-28

申请号：US09484606

申请日：2000-01-18

申请人： Dawn M. Hopper ,  Minh Van Ngo ,  David K. Foote

发明人： Dawn M. Hopper ,  Minh Van Ngo ,  David K. Foote

IPC分类号： H01L21302

CPC分类号： H01L21/3185 ,  H01L21/32139 ,  Y10S438/952

摘要： A process for fabricating a semiconductor device using an ARC layer includes the formation of a silicon-rich silicon nitride material to provide an anti-reflective layer over a electrically conductive or semiconductor surface. The silicon-rich silicon nitride material is plasma deposited to provide a material having a desired refractive index, thickness uniformity, and density. The process includes the formation of a device layer on a semiconductor substrate. The device layer includes at least a silicon layer and a silicon oxide layer. A silicon-rich silicon nitride layer is formed to overlie the device layer. The silicon-rich silicon nitride material can be selectively etched, such that the silicon material and the silicon oxide material in the underlying device layer are not substantially etched.

摘要翻译： 使用ARC层制造半导体器件的方法包括形成富硅的氮化硅材料，以在导电或半导体表面上提供抗反射层。 富硅氮化硅材料被等离子体沉积以提供具有期望的折射率，厚度均匀性和密度的材料。 该方法包括在半导体衬底上形成器件层。 器件层至少包括硅层和氧化硅层。 形成富含硅的氮化硅层以覆盖器件层。 可以选择性地蚀刻富硅的氮化硅材料，使得底层器件层中的硅材料和氧化硅材料基本上不被蚀刻。

公开(公告)号：US06677679B1

公开(公告)日：2004-01-13

申请号：US09776749

申请日：2001-02-06

申请人： Lu You ,  Fei Wang ,  Dawn M. Hopper

发明人： Lu You ,  Fei Wang ,  Dawn M. Hopper

IPC分类号： H01L214763

CPC分类号： H01L21/76832 ,  H01L21/76802 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76834

摘要： A semiconductor device includes a first metallization level, a first diffusion barrier layer, a first etch stop layer, a second etch top layer, a dielectric layer and an opening extending through the dielectric layer, the first and second etch stop layers, and the first diffusion barrier layer. The first diffusion barrier layer is disposed over the first metallization level. The second etch stop layer is disposed over the first diffusion barrier layer, and the first etch stop layer is disposed on the second etch stop layer with a first interface therebetween. The dielectric layer is disposed over the first etch stop layer. The opening can also have rounded corners. A sidewall diffusion barrier layer can be disposed on sidewalls of the opening, and the sidewall diffusion barrier layer is formed from the same material as the first diffusion barrier layer. The first etch stop layer and the barrier diffusion layer can be formed from silicon nitride, and the second etch stop layer can be formed from silicon oxide. Metal within the opening forms a second metal feature, and the metal can comprise copper or a copper alloy. A method of manufacturing the semiconductor device is also disclosed.

摘要翻译： 半导体器件包括第一金属化水平，第一扩散阻挡层，第一蚀刻停止层，第二蚀刻顶层，介电层和延伸穿过介电层的开口，第一和第二蚀刻停止层以及第一蚀刻停止层 扩散阻挡层。 第一扩散阻挡层设置在第一金属化层上。 第二蚀刻停止层设置在第一扩散阻挡层上，并且第一蚀刻停止层设置在第二蚀刻停止层上，其间具有第一界面。 介电层设置在第一蚀刻停止层上。 开口也可以有圆角。 侧壁扩散阻挡层可以设置在开口的侧壁上，并且侧壁扩散阻挡层由与第一扩散阻挡层相同的材料形成。 第一蚀刻停止层和阻挡扩散层可以由氮化硅形成，并且第二蚀刻停止层可以由氧化硅形成。 开口内的金属形成第二金属特征，金属可以包括铜或铜合金。 还公开了制造半导体器件的方法。

公开(公告)号：US06599839B1

公开(公告)日：2003-07-29

申请号：US09773906

申请日：2001-02-02

申请人： Calvin T. Gabriel ,  Lynne A. Okada ,  Dawn M. Hopper ,  Suzette K. Pangrle ,  Fei Wang

发明人： Calvin T. Gabriel ,  Lynne A. Okada ,  Dawn M. Hopper ,  Suzette K. Pangrle ,  Fei Wang

IPC分类号： H01L21302

CPC分类号： H01L21/31138 ,  C23F1/12 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76802

摘要： A composite layer comprising a non-homogenous layer is etched by continuously varying a process parameter, such as the amount of reactive agent in an etchant mixture. Embodiments include etching a silicon oxide film having a varying concentration of carbon through the film with an etchant mixture containing a fluorinated organic, oxygen and an inert gas and continuously increasing and/or decreasing the amount of oxygen in the etchant mixture during etching through the silicon oxide film.

摘要翻译： 通过连续改变工艺参数（例如蚀刻剂混合物中的反应剂的量）蚀刻包含非均匀层的复合层。 实施例包括用含有氟化有机物，氧气和惰性气体的蚀刻剂混合物蚀刻具有不同浓度碳的氧化硅膜，并且在通过硅蚀刻过程中连续增加和/或减少蚀刻剂混合物中的氧气量 氧化膜。

公开(公告)号：US06656830B1

公开(公告)日：2003-12-02

申请号：US09777695

申请日：2001-02-07

申请人： Ramkumar Subramanian ,  Dawn M. Hopper ,  Fei Wang ,  Lynne A. Okada

发明人： Ramkumar Subramanian ,  Dawn M. Hopper ,  Fei Wang ,  Lynne A. Okada

IPC分类号： H01L214763

CPC分类号： H01L21/76843 ,  H01L21/76807

摘要： The dimensional accuracy of trench formation and, hence, metal line width, in damascene processing is improved by employing a silicon carbide middle etch stop layer/ARC. Embodiments include via first-trench last dual damascene techniques employing a silicon carbide middle etch stop layer/ARC having an extinction coefficient (k) of about −0.10 to about −0.60.

摘要翻译： 通过采用碳化硅中间蚀刻停止层/ ARC，提高了镶嵌加工中沟槽形成的尺寸精度以及因此的金属线宽度。 实施例包括使用具有约-0.10至约-0.60的消光系数（k）的碳化硅中蚀刻停止层/ ARC的第一沟槽最后双镶嵌技术。

公开(公告)号：US06576545B1

公开(公告)日：2003-06-10

申请号：US09819987

申请日：2001-03-29

申请人： Dawn M. Hopper ,  Lu You ,  Minh Van Ngo

发明人： Dawn M. Hopper ,  Lu You ,  Minh Van Ngo

IPC分类号： H01L214763

CPC分类号： H01L21/76829 ,  H01L21/76807

摘要： Degradation of fluorine-doped silica glass low-k inter-layer dielectrics during fabrication is significantly reduced and resolution of submicron features is improved by the formation of dual nature capping/ARC layers on inter-layer dielectric films. The capping/ARC layer is formed in-situ on a fluorine-doped silica glass inter-layer dielectric. The in-situ formation of the capping/ARC layer provides a strongly adhered capping/ARC layer, formed with fewer processing steps than conventional capping and ARC layers.

摘要翻译： 通过在层间电介质膜上形成双重性能覆盖/ ARC层，制造过程中氟掺杂二氧化硅玻璃低k层间电介质的退化显着降低，亚微米特征的分辨率得到改善。 封盖/ ARC层在氟掺杂石英玻璃层间电介质上原位形成。 封盖/ ARC层的原位形成提供了强烈粘附的封盖/ ARC层，其形成与传统封盖和ARC层相比较少的处理步骤。