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    System, Apparatus And Method For Multi-Cacheline Small Object Memory Tagging
    1.
    发明申请
    System, Apparatus And Method For Multi-Cacheline Small Object Memory Tagging 审中-公开

    公开(公告)号：US20190108130A1

    公开(公告)日：2019-04-11

    申请号：US16205508

    申请日：2018-11-30

    申请人： David M. Durham ,  Ron Gabor ,  Rajat Agarwal

    发明人： David M. Durham ,  Ron Gabor ,  Rajat Agarwal

    IPC分类号： G06F12/0895

    摘要： In one embodiment, a method includes: in response to a sub-cacheline memory access request, receiving a data-line from a memory coupled to a processor; receiving tag information included in metadata associated with the data-line from the memory; determining, in a memory controller, whether a first tag identifier of the tag information matches a tag portion of an address of the memory line associated with the sub-cacheline memory access request, and in response to determining a match, storing a first portion of the data-line associated with the first tag identifier in a cache line of a cache of the processor, the first portion a sub-cacheline width. This method allows data lines stored in memory associated with multiple different tag metadata to be divided into multiple cachelines comprising the sub-cacheline data associated with a particular metadata address tag. Other embodiments are described and claimed.

    Acceleration threads on idle OS-visible thread execution units
    2.
    发明授权
    Acceleration threads on idle OS-visible thread execution units 有权
    空闲OS可见线程执行单元上的加速线程

    公开(公告)号：US09003421B2

    公开(公告)日：2015-04-07

    申请号：US11288823

    申请日：2005-11-28

    申请人： Ron Gabor ,  Gad Sheaffer ,  Avi Mendelson ,  Uri C. Weiser ,  Hong Wang

    发明人： Ron Gabor ,  Gad Sheaffer ,  Avi Mendelson ,  Uri C. Weiser ,  Hong Wang

    IPC分类号： G06F9/46 ,  G06F9/30 ,  G06F9/48 ,  G06F9/50

    CPC分类号： G06F9/4843 ,  G06F9/461 ,  G06F9/5027 ,  G06F2209/5018

    摘要： Disclosed are embodiments of a system, methods and mechanism for using idle thread units to perform acceleration threads that are transparent to the operating system. When the operating system scheduler has no work to schedule on the idle thread units, the operating system may issue a halt or monitor/mwait or other instruction to place the thread unit into an idle state. While the thread unit is idle, from the operating system perspective, the thread unit may be utilized to perform speculative acceleration threads in order to accelerate threads running on non-idle thread units. The context of the idle thread unit is saved prior to execution of the acceleration thread and is restored when the operating system requires use of the thread unit. The acceleration threads are transparent to the operating system. Other embodiments are also described and claimed.

    摘要翻译： 公开了使用空闲螺纹单元执行对操作系统透明的加速度线程的系统，方法和机构的实施例。 当操作系统调度器没有在空闲线程单元上进行调度时，操作系统可以发出停止或监视/等待或其他指令来将线程单元置于空闲状态。 当线程单元处于空闲状态时，从操作系统的角度来看，线程单元可用于执行推测加速线程，以加速在非空闲线程单元上运行的线程。 空闲线程单元的上下文在执行加速线程之前被保存，并且当操作系统需要使用线程单元时被恢复。 加速线程对操作系统是透明的。 还描述和要求保护其他实施例。

    Performance simulation of multiprocessor systems
    6.
    发明授权
    Performance simulation of multiprocessor systems 有权
    多处理器系统的性能仿真

    公开(公告)号：US07650273B2

    公开(公告)日：2010-01-19

    申请号：US11231619

    申请日：2005-09-21

    申请人： Ron Gabor ,  Nathaniel Leibowitz ,  Meir Tsadik ,  Yoram Kulbak

    发明人： Ron Gabor ,  Nathaniel Leibowitz ,  Meir Tsadik ,  Yoram Kulbak

    IPC分类号： G06F9/44

    CPC分类号： G06F11/3457 ,  G06F17/5022

    摘要： An embodiment of the present invention is a technique to simulate performance of a multi-core system. A micro-architecture effect is estimated from each core in the multi-core system. A model of a memory hierarchy associated with each core is simulated. The simulated model of the memory hierarchy is superpositioned on the estimated micro-architecture effect to produce a performance figure for the multi-core system.

    摘要翻译： 本发明的一个实施例是一种模拟多核系统性能的技术。 从多核系统中的每个核心估计微架构效应。 模拟与每个核心相关联的内存层次的模型。 存储器层次的模拟模型叠加在估计的微架构效应上，以产生多核系统的性能指标。

    Power aware software pipelining for hardware accelerators
    7.
    发明申请
    Power aware software pipelining for hardware accelerators 有权
    功率感知软件流水线用于硬件加速器

    公开(公告)号：US20080148076A1

    公开(公告)日：2008-06-19

    申请号：US11642128

    申请日：2006-12-19

    申请人： Ron Gabor ,  Hong Jiang ,  Alon Naveh ,  Doron Rajwan ,  James Varga ,  Gady Yearim ,  Yuval Yosef

    发明人： Ron Gabor ,  Hong Jiang ,  Alon Naveh ,  Doron Rajwan ,  James Varga ,  Gady Yearim ,  Yuval Yosef

    IPC分类号： G06F1/28

    CPC分类号： G06F1/3203

    摘要： Forming a plurality of pipeline orderings, each pipeline ordering comprising one of a sequential, a parallel, or a sequential and parallel combination of a plurality of stages of a pipeline, analyzing the plurality of pipeline orderings to determine a total power of each of the orderings, and selecting one of the plurality of pipeline orderings based on the determined total power of each of the plurality of pipeline orderings.

    摘要翻译： 形成多个流水线排序，每个流水线排序包括流水线的多个阶段的顺序，并行或顺序和并行组合中的一个，分析多个流水线排序以确定每个排序的总功率 并且基于所确定的多个流水线排序中的每一个的总功率来选择多个流水线排序中的一个。

    Local power gate (LPG) interfaces for power-aware operations
    10.
    发明授权
    Local power gate (LPG) interfaces for power-aware operations 有权
    用于电源感知操作的本地电源门（LPG）接口

    公开(公告)号：US09519324B2

    公开(公告)日：2016-12-13

    申请号：US14225612

    申请日：2014-03-26

    申请人： Michael Mishaeli ,  Ron Gabor ,  Robert C. Valentine ,  Alex Gerber ,  Zeev Sperber

    发明人： Michael Mishaeli ,  Ron Gabor ,  Robert C. Valentine ,  Alex Gerber ,  Zeev Sperber

    IPC分类号： G06F1/32 ,  G06F9/22

    CPC分类号： G06F1/3206 ,  G06F1/3287 ,  G06F9/22 ,  Y02D10/171

    摘要： Technologies for local power gate (LPG) interfaces for power-aware operations are described. A processor includes locally-gated circuitry of a core, main core circuitry of the core, the main core, and local power gate (LPG) hardware. The LPG hardware is to power gate the locally-gated circuitry according to local power states of the LPG hardware. The main core decodes a first instruction of a set of instructions to perform a first power-aware operation of a specified length, including computing an execution code path for execution. The main core monitors a current local power state of the LPG hardware, selects one of the code paths based on the current local power state, the specified length, and a specified threshold, and issues a hint to the LPG hardware to power up the locally-gated circuitry and continues execution of the first power-aware operation without waiting for the locally-gated circuitry to be powered up.

    摘要翻译： 描述了用于功率感知操作的本地电源门（LPG）接口的技术。 处理器包括核心的本地门控电路，核心的主核心电路，主核心和本地电源门（LPG）硬件。 LPG硬件根据LPG硬件的本地电源状态为本地门控电路供电。 主核心解码一组指令的第一指令以执行指定长度的第一功率感知操作，包括计算用于执行的执行代码路径。 主核心监控LPG硬件的当前本地电源状态，根据当前本地电源状态，指定长度和指定的阈值选择其中一条代码路径，并向LPG硬件发出提示，以启动本地 并且继续执行第一功率感知操作，而不等待本地门控电路被加电。