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    Utilization of Processor Capacity at Low Operating Frequencies
    1.
    发明申请
    Utilization of Processor Capacity at Low Operating Frequencies 有权
    处理器容量在低工作频率下的利用率

    公开(公告)号：US20150095674A1

    公开(公告)日：2015-04-02

    申请号：US14039368

    申请日：2013-09-27

    Applicant: Ruchira Sasanka ,  Alexander Gendler ,  Udi Sherel

    Inventor： Ruchira Sasanka ,  Alexander Gendler ,  Udi Sherel

    IPC: G06F1/32

    CPC classification number: G06F1/3296 ,  G06F1/266 ,  G06F1/324 ,  G06F12/0223 ,  G06F12/084 ,  G06F2212/62 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D50/20

    Abstract: In an embodiment, a processor includes one or more cores including a first core operable at an operating voltage between a minimum operating voltage and a maximum operating voltage. The processor also includes a power control unit including first logic to enable coupling of ancillary logic to the first core responsive to the operating voltage being less than or equal to a threshold voltage, and to disable the coupling of the ancillary logic to the first core responsive to the operating voltage being greater than the threshold voltage. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，处理器包括一个或多个核，包括可在最小工作电压和最大工作电压之间的工作电压下工作的第一核。 处理器还包括功率控制单元，其包括第一逻辑，以便响应于小于或等于阈值电压的工作电压来使辅助逻辑耦合到第一核心，并且禁用辅助逻辑与第一核心的耦合响应 使工作电压大于阈值电压。 描述和要求保护其他实施例。

    Method, apparatus, system creating, executing and terminating mini-threads
    4.
    发明授权
    Method, apparatus, system creating, executing and terminating mini-threads 有权
    方法，设备，系统创建，执行和终止微型线程

    公开(公告)号：US09323528B2

    公开(公告)日：2016-04-26

    申请号：US13722588

    申请日：2012-12-20

    Applicant: Ruchira Sasanka

    Inventor： Ruchira Sasanka

    IPC: G06F9/30 ,  G06F9/38

    CPC classification number: G06F9/3009 ,  G06F9/30098 ,  G06F9/30189 ,  G06F9/3851 ,  G06F9/3877

    Abstract: Described herein are mechanisms for creating, executing, and terminating mini-threads. A processor executes instructions with a primary thread in a first execution mode, and to execute an instruction to create a secondary mini-thread that is associated with a first subset of registers and associates the primary thread with a second subset of the registers during a second execution mode. During the second execution mode, the primary thread operates as a primary mini-thread.

    Abstract translation: 这里描述了用于创建，执行和终止微型线程的机制。 处理器以第一执行模式执行具有主线程的指令，并且执行指令以创建与第一寄存器子集相关联的辅助微线程，并且在第二执行模式期间将主线程与寄存器的第二子集相关联 执行模式。 在第二执行模式期间，主线程作为主要的微型线程运行。

    AUTOMATIC IDENTIFICATION AND GENERATION OF NON-TEMPORAL STORE AND LOAD OPERATIONS IN A DYNAMIC OPTIMIZATION ENVIRONMENT
    5.
    发明申请
    AUTOMATIC IDENTIFICATION AND GENERATION OF NON-TEMPORAL STORE AND LOAD OPERATIONS IN A DYNAMIC OPTIMIZATION ENVIRONMENT 审中-公开

    公开(公告)号：US20180189040A1

    公开(公告)日：2018-07-05

    申请号：US15393931

    申请日：2016-12-29

    Applicant: Ruchira Sasanka

    Inventor： Ruchira Sasanka

    IPC: G06F9/45 ,  G06F9/455

    CPC classification number: G06F8/4442 ,  G06F9/30043 ,  G06F9/45516 ,  G06F11/34

    Abstract: Techniques are disclosed to identify a frequently-executed region of code during runtime execution of the code, generate initial profiling code for the frequently-executed region of code, cause the initial profiling code to be executed for a minimum number of processing cycles of the computer, and identify replacement candidate store instruction(s) that store a value that is not read by the frequently-executed region of code during execution of the initial profiling code. Replacement candidate load instruction(s) may also be identified that load a value that is not stored or loaded by the frequently-executed region of code during execution of the initial profiling code. Optimized code for the frequently-executed region of code may be generated by replacing each of the replacement candidate store or load instructions(s) with a non-temporal store or load instruction. The optimized code may be executed instead of the frequently-executed region of code during subsequent runtime execution.

    ANALYZING POTENTIAL BENEFITS OF VECTORIZATION
    7.
    发明申请
    ANALYZING POTENTIAL BENEFITS OF VECTORIZATION 有权
    分析潜在收益的潜在优势

    公开(公告)号：US20140258677A1

    公开(公告)日：2014-09-11

    申请号：US13997140

    申请日：2013-03-05

    Applicant: Ruchira Sasanka ,  Jeffrey J. Cook ,  Abhinav Das ,  Jayaram Bobba ,  Michael R. Greenfield ,  Suresh Srinivas

    Inventor： Ruchira Sasanka ,  Jeffrey J. Cook ,  Abhinav Das ,  Jayaram Bobba ,  Michael R. Greenfield ,  Suresh Srinivas

    IPC: G06F9/30

    CPC classification number: G06F8/41 ,  G06F8/456

    Abstract: Embodiments of computer-implemented methods, systems, computing devices, and computer-readable media (transitory and non-transitory) are described herein for analyzing execution of a plurality of executable instructions and, based on the analysis, providing an indication of a benefit to be obtained by vectorization of at least a subset of the plurality of executable instructions. In various embodiments, the analysis may include identification of the subset of the plurality of executable instructions suitable for conversion to one or more single-instruction multiple-data (“SIMD”) instructions.

    Abstract translation: 本文描述了计算机实现的方法，系统，计算设备和计算机可读介质（暂时性和非暂时性）的实施例，用于分析多个可执行指令的执行，并且基于该分析，提供对 可以通过对多个可执行指令的至少一个子集进行向量化来获得。 在各种实施例中，分析可以包括识别适合于转换成一个或多个单指令多数据（“SIMD”）指令的多个可执行指令的子集。

    SYSTEM, APPARATUS AND METHOD FOR TRANSLATING VECTOR INSTRUCTIONS
    8.
    发明申请
    SYSTEM, APPARATUS AND METHOD FOR TRANSLATING VECTOR INSTRUCTIONS 有权
    用于转换矢量指令的系统，装置和方法

    公开(公告)号：US20130283022A1

    公开(公告)日：2013-10-24

    申请号：US13993603

    申请日：2011-12-06

    Applicant: Ruchira Sasanka

    Inventor： Ruchira Sasanka

    IPC: G06F9/30

    CPC classification number: G06F9/30181 ,  G06F9/3001 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30076 ,  G06F9/3017 ,  G06F9/30174

    Abstract: Vector translation instructions are used to demarcate the beginning and the end of a code region to be translated. The code region includes a first set of vector instructions defined in an instruction set of a source processor. A processor receives the vector translation instructions and the demarcated code region, and translates the code region into translated code. The translated code includes a second set of vector instructions defined in an instruction set of a target processor. The translated code is executed by the target processor to produce a result value, the result value being the same as an original result value produced by the source processor executing the code region. The target processor stores the result value at a location that is not a vector register, the location being the same as an original location used by the source processor to store the original result value.

    Abstract translation: 矢量翻译指令用于划分要翻译的代码区域的开始和结束。 代码区域包括在源处理器的指令集中定义的第一组向量指令。 处理器接收向量转换指令和划分的代码区域，并将代码区域转换为翻译代码。 翻译的代码包括在目标处理器的指令集中定义的第二组矢量指令。 翻译后的代码由目标处理器执行以产生结果值，结果值与由执行代码区域的源处理器产生的原始结果值相同。 目标处理器将结果值存储在不是向量寄存器的位置处，该位置与源处理器用于存储原始结果值的原始位置相同。

    System, apparatus and method for translating vector instructions
    9.
    发明授权
    System, apparatus and method for translating vector instructions 有权
    用于翻译矢量指令的系统，装置和方法

    公开(公告)号：US09424042B2

    公开(公告)日：2016-08-23

    申请号：US13993603

    申请日：2011-12-06

    Applicant: Ruchira Sasanka

    Inventor： Ruchira Sasanka

    IPC: G06F9/30

    CPC classification number: G06F9/30181 ,  G06F9/3001 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30076 ,  G06F9/3017 ,  G06F9/30174

    Abstract: Vector translation instructions are used to demarcate the beginning and the end of a code region to be translated. The code region includes a first set of vector instructions defined in an instruction set of a source processor. A processor receives the vector translation instructions and the demarcated code region, and translates the code region into translated code. The translated code includes a second set of vector instructions defined in an instruction set of a target processor. The translated code is executed by the target processor to produce a result value, the result value being the same as an original result value produced by the source processor executing the code region. The target processor stores the result value at a location that is not a vector register, the location being the same as an original location used by the source processor to store the original result value.

    Abstract translation: 矢量翻译指令用于划分要翻译的代码区域的开始和结束。 代码区域包括在源处理器的指令集中定义的第一组向量指令。 处理器接收向量转换指令和划分的代码区域，并将代码区域转换为翻译代码。 翻译的代码包括在目标处理器的指令集中定义的第二组矢量指令。 翻译后的代码由目标处理器执行以产生结果值，结果值与由执行代码区域的源处理器产生的原始结果值相同。 目标处理器将结果值存储在不是向量寄存器的位置处，该位置与源处理器用于存储原始结果值的原始位置相同。

    TRACKING CONTROL FLOW OF INSTRUCTIONS
    10.
    发明申请
    TRACKING CONTROL FLOW OF INSTRUCTIONS 有权
    跟踪指令的控制流程

    公开(公告)号：US20140281424A1

    公开(公告)日：2014-09-18

    申请号：US13834049

    申请日：2013-03-15

    Applicant: Jayaram Bobba ,  Ruchira Sasanka ,  Jeffrey J. Cook ,  Abhinav Das ,  Arvind Krishnaswamy ,  David J. Sager ,  Jason M. Agron

    Inventor： Jayaram Bobba ,  Ruchira Sasanka ,  Jeffrey J. Cook ,  Abhinav Das ,  Arvind Krishnaswamy ,  David J. Sager ,  Jason M. Agron

    IPC: G06F9/30

    CPC classification number: G06F9/3005 ,  G06F8/433 ,  G06F11/0715 ,  G06F11/0721 ,  G06F11/076 ,  G06F11/3466

    Abstract: A mechanism for tracking the control flow of instructions in an application and performing one or more optimizations of a processing device, based on the control flow of the instructions in the application, is disclosed. Control flow data is generated to indicate the control flow of blocks of instructions in the application. The control flow data may include annotations that indicate whether optimizations may be performed for different blocks of instructions. The control flow data may also be used to track the execution of the instructions to determine whether an instruction in a block of instructions is assigned to a thread, a process, and/or an execution core of a processor, and to determine whether errors have occurred during the execution of the instructions.

    Abstract translation: 公开了一种用于跟踪应用程序中的指令的控制流程并基于应用程序中的指令的控制流程执行处理设备的一个或多个优化的机制。 生成控制流数据以指示应用程序中的指令块的控制流程。 控制流数据可以包括指示是否可以针对不同的指令块执行优化的注释。 控制流数据还可以用于跟踪指令的执行以确定指令块中的指令是否被分配给处理器的线程，进程和/或执行核心，并且确定错误是否具有 在执行指令期间发生。

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