公开(公告)号：US06281717B1

公开(公告)日：2001-08-28

申请号：US09457628

申请日：1999-12-08

申请人： David M. Thomas ,  Richard J. Reay

发明人： David M. Thomas ,  Richard J. Reay

IPC分类号： G11C2702

CPC分类号： G11C27/026 ,  G11C27/024 ,  H03K17/063

摘要： Circuits and methods are provided that compensate for dynamic errors caused by voltage drops across a switch coupled in series with a capacitor in an electrical circuit such as a track-and-hold circuit. In such circuits, the capacitor should provide the same voltage as a signal coupled to the switch, but does not because of the switch voltage drop. The switch can be, for example, a MOSFET or more particularly a CMOS device. Dynamic errors are compensated for by measuring the voltage drop across the switch and then effectively adding the measured voltage drop to a voltage provided by the capacitor.

摘要翻译： 提供电路和方法，其补偿由诸如轨道和保持电路之类的电路中与电容器串联耦合的开关上的电压降引起的动态误差。 在这样的电路中，电容器应该提供与耦合到开关的信号相同的电压，但不是因为开关电压降。 该开关可以是例如MOSFET或更具体的CMOS器件。 通过测量开关两端的电压降来补偿动态误差，然后将测得的电压降有效地加到由电容器提供的电压上。

公开(公告)号：US20120013389A1

公开(公告)日：2012-01-19

申请号：US12949722

申请日：2010-11-18

申请人： David M. Thomas ,  Richard J. Reay

发明人： David M. Thomas ,  Richard J. Reay

IPC分类号： H03K17/04

CPC分类号： G05F3/262

摘要： In the preferred embodiment, a current source is switchable between two precisely defined output currents. A terminal of a coupling capacitor is coupled to the gate of an output MOSFET. The other terminal of the capacitor is switched between two reference voltages to toggle the MOSFET to output the selected one of the two currents. A switchable bias voltage source is coupled to the gate only during the on state of the MOSFET to set the gate voltage of the MOSFET. The current output of the current source is quickly and accurately changed. A reference MOSFET is not directly coupled to the output MOSFET, so there are no slow settling components coupled to the gate of the output MOSFET.

摘要翻译： 在优选实施例中，电流源可在两个精确限定的输出电流之间切换。 耦合电容的端子耦合到输出MOSFET的栅极。 电容器的另一个端子在两个参考电压之间切换，以切换MOSFET以输出两个电流中选择的一个。 只有在MOSFET的导通状态下才可将可切换偏置电压源耦合到栅极，以设置MOSFET的栅极电压。 电流源的当前输出快速准确地改变。 参考MOSFET不直接耦合到输出MOSFET，因此没有与输出MOSFET的栅极耦合的缓慢的稳定元件。

公开(公告)号：US6124818A

公开(公告)日：2000-09-26

申请号：US176397

申请日：1998-10-21

申请人： David M. Thomas ,  Richard J. Reay

发明人： David M. Thomas ,  Richard J. Reay

IPC分类号： H03M1/16 ,  H03M1/46 ,  H03M1/12 ,  H03M1/38

CPC分类号： H03M1/164 ,  H03M1/468

摘要： Improved pipelined successive approximation analog-to-digital converter circuits are provided. Some embodiments of the present invention comprises two stages in which a first portion of the total bits are evaluated in the first stage of the circuit and then the residue is passed to the second stage of the circuit that evaluates the remaining portion. By operating both stages simultaneously, the throughput is increased. These embodiments utilize two matched buffers to isolate the first and second stages from switching errors of a sampling circuit and the loading effects of comparators associated with the two stages. In another embodiment, upon completion of the conversion of the MSBs, the remaining input signal or residue signal is amplified by a preamp and the output is subsequently sampled by a residue sample and hold circuit (S/H). After the residue is sampled by the residue S/H, the second stage begins to solve the least significant bits (LSBs). The second stage is a matched copy of the first stage. Furthermore, if the CDACs and the preamps corresponding to the two stages are matched, the actual value of the preamp gain does not affect converter linearity. In yet another embodiment, a single preamp buffer is switched between the first and second stages. The preamp provides buffering of the top plates of the capacitor array from the residue sampling switch.

摘要翻译： 提供了改进的流水线逐次逼近模数转换器电路。 本发明的一些实施例包括两个阶段，其中在电路的第一阶段评估总比特的第一部分，然后将残余物传递到评估剩余部分的电路的第二阶段。 通过同时操作两个阶段，增加了吞吐量。 这些实施例利用两个匹配的缓冲器来隔离第一级和第二级与采样电路的开关误差和与两级相关联的比较器的负载效应。 在另一个实施例中，在完成MSB的转换之后，剩余的输入信号或残留信号被前置放大器放大，随后输出被剩余采样和保持电路（S / H）采样。 残差采用残差S / H，第二阶段开始求解最低有效位（LSB）。 第二阶段是第一阶段的匹配副本。 此外，如果对应于两级的CDAC和前置放大器匹配，则前置放大器增益的实际值不会影响转换器的线性度。 在另一个实施例中，单个前置放大器缓冲器在第一和第二级之间切换。 前置放大器从残留采样开关提供电容器阵列的顶板的缓冲。

公开(公告)号：US5612698A

公开(公告)日：1997-03-18

申请号：US375378

申请日：1995-01-17

申请人： Richard J. Reay

发明人： Richard J. Reay

IPC分类号： H03M1/18 ,  H03M1/52 ,  H03M1/50

CPC分类号： H03M1/181 ,  H03M1/52

摘要： A current-input, autoscaling, dual-slope A/D converter includes means for adjusting the integration period of the input current to effectively adjust a scale factor associated with the converter. An integrator circuit of the converter includes means for precharging an integration capacitor of the integrator circuit to an off-set voltage associated with an amplifier of the integrator circuit, so as to effectively eliminate integration error due to the off-set voltage. A PMOS switching transistor associated with precharging the integration capacitor is formed in an n-well biased to a voltage approximately equal in magnitude to a voltage held across the integration capacitor, so as to minimized leakage current from the capacitor through the PMOS switching transistor.

摘要翻译： 电流输入自动缩放双斜率A / D转换器包括用于调整输入电流的积分周期以有效地调整与转换器相关联的比例因子的装置。 转换器的积分电路包括用于将积分电路的积分电容器预充电到与积分电路的放大器相关的偏置电压的装置，以便有效地消除由于偏置电压引起的积分误差。 与积分电容器预充电相关联的PMOS开关晶体管形成在n阱中，该n阱被偏置到与整流电容器两端保持的电压大致相等的电压，以便使来自电容器的PMOS开关晶体管的漏电流最小化。

公开(公告)号：US5600174A

公开(公告)日：1997-02-04

申请号：US321299

申请日：1994-10-11

申请人： Richard J. Reay ,  Erno H. Klaassen

发明人： Richard J. Reay ,  Erno H. Klaassen

IPC分类号： G01F1/684 ,  G01K7/01 ,  H01L29/10 ,  H01L31/058 ,  H01L29/06

CPC分类号： H01L29/1079 ,  G01F1/6845 ,  G01K7/015

摘要： Temperature-sensitive transducers and other circuitry are manufactured by an electrochemical post-processing etch on an integrated circuit fabricated using a conventional CMOS process. Tetramethyl ammonium hydroxide or another anisotropic etchant having similar characterisics is used to selectively etch exposed front-side regions of a p-type silicon substrate, leaving n-type wells suspended from oxide beams. Circuits in the n-wells are thermally and electrically insulated from the substrate.

摘要翻译： 温度敏感传感器和其他电路通过在使用常规CMOS工艺制造的集成电路上的电化学后处理蚀刻来制造。 使用四甲基氢氧化铵或具有相似特性的另一种各向异性蚀刻剂来选择性地蚀刻p型硅衬底的暴露的前侧区域，留下n型阱悬浮在氧化物束上。 n阱中的电路与基板热电绝缘。