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1.发明授权Apparatus and method for synchronization of access to main memory signal groups in a multiprocessor data processing system 失效用于在多处理器数据处理系统中访问主存储器信号组的同步的装置和方法
公开(公告)号：US5291581A
公开(公告)日：1994-03-01
申请号：US844968
申请日：1992-02-28
CPC分类号： G06F9/52 , G06F15/8069
摘要： In a multiprocessor data processing unit, a data element in the main memory unit, that has system wide significance, can have a requirement that this data element be altered in a controlled manner. Because other data processing units can have access to this data element, the alteration of the data element must be synchronized so the other data processing units are not in the process of altering the same data element simultaneously. The present invention includes an instruction that acquires access to an interlock signal in the main memory unit and initiates an interlock in the main memory unit, thereby excluding other data processing units from gaining access to the interlock signal simultaneously. The instruction causes the data element related to the interlock signal to be transferred to the data processing unit where the data element is saved, can be entered in mask apparatus and then have a quantity added thereto. The altered data element is returned to the main memory unit location and the main memory interlock signal is released, thereby completing the instruction.
摘要翻译： 在多处理器数据处理单元中，具有系统广泛意义的主存储单元中的数据元素可以要求以受控的方式改变该数据元素。 因为其他数据处理单元可以访问该数据元素，所以数据元素的改变必须被同步，以便其他数据处理单元不会同时改变相同的数据元素。 本发明包括获取对主存储器单元中的联锁信号的访问并且在主存储器单元中启动互锁的指令，从而排除其他数据处理单元以同时访问互锁信号。 该指令使与互锁信号相关的数据元素被传送到数据元素被保存的数据处理单元，可以进入掩模装置，然后添加一个数量。 更改的数据元素返回到主存储器单元位置，并且主存储器互锁信号被释放，从而完成指令。
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2.发明授权Method for synchronization of arithmetic exceptions in central processing units having pipelined execution units simultaneously executing instructions 失效在具有流水线执行单元的中央处理单元中同步执行指令的算术异常的同步方法
公开(公告)号：US5341482A
公开(公告)日：1994-08-23
申请号：US995341
申请日：1992-12-22
IPC分类号： G06F9/38 , G06F9/30 , G06F9/34 , G06F13/376
CPC分类号： G06F9/3861
摘要： An instruction eases exception handling in a data processing system having one or more parallel pipelined execution units by permitting the central processing unit to complete instructions currently being processed by the execution units, but preventing further instructions from being initiated until all currently executing instructions have been completed and all outstanding exception conditions have been resolved. After all the instructions preceding the DRAIN instruction of the present invention in the program instruction sequence have been executed, the central processing unit can continue to execute the sequential program instructions when no arithmetic exception has been identified, or can invoke an exception handling procedure when an arithmetic exception has been identified. The instruction is typically positioned in an instruction sequence after an instruction that has high degree of probability of resulting in the identification of an arithmetic exception condition. The DRAIN instruction permits the source of the exception to be localized and permits the response to all arithmetic exceptions associated with instructions initiated before the DRAIN instruction, but identified after the execution of the DRAIN instruction, to be handled in the same context environment in which the instruction was initiated.
摘要翻译： 一种指令通过允许中央处理单元完成由执行单元正在处理的指令，但是在所有当前执行的指令已经完成之前阻止进一步的指令被启动，从而简化了具有一个或多个并行流水线执行单元的数据处理系统中的异常处理 所有突出的例外情况都已经解决。 在程序指令序列中本发明的DRAIN指令之前的所有指令已被执行之后，当没有识别出算术异常时，中央处理单元可以继续执行顺序程序指令，或者当调用异常处理程序时 算术异常已被识别。 指令通常位于指令序列之后，该指令具有导致算术异常条件的识别的高概率概率。 DRAIN指令允许异常源被本地化，并且允许对在DRAIN指令之前发起的指令相关联的所有算术异常进行响应，但在执行DRAIN指令之后识别，以在相同的上下文环境中处理，其中 教学开始了。
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3.发明授权Apparatus and method for control of asynchronous program interrupt events in a data processing system 失效用于在数据处理系统中控制异步程序中断事件的装置和方法
公开(公告)号：US5148544A
公开(公告)日：1992-09-15
申请号：US704710
申请日：1991-05-17
CPC分类号： G06F9/4812 , G06F9/30076
摘要： In a data procesing system having a kernel mode (i.e., for executing privileged instructions) and a user mode of operation, apparatus for responding to interrupt conditions includes a first register, subject to the control of the currently executing program for enabling the generation of a mode-related interrupt signal and includes a second register for indicating the presence of a pending mode-related interrupt condition and a third register for requesting a mode-related interrupt be entered in the second register. The mode of operation and the enable and pending interrupt condition registers are monitored and when the signals in the two registers have the appropriate relationship, an interrupt signal is generated to which a control program will respond. The contents of the first register can be controlled by the currently executing program which can control the enabling signal for the currently executing mode. The pending interrupt condition and the request registers may be accessed only from the privileged mode of operation.
摘要翻译： 在具有内核模式（即，用于执行特许指令）和用户操作模式的数据处理系统中，用于响应中断条件的装置包括第一寄存器，受到当前正在执行的程序的控制以使能生成 模式相关中断信号，并且包括用于指示存在待决模式相关中断条件的第二寄存器，并且用于请求模式相关中断的第三寄存器被输入到第二寄存器中。 监视操作模式和使能和待处理中断条件寄存器，并且当两个寄存器中的信号具有适当的关系时，产生一个控制程序将响应的中断信号。 第一寄存器的内容可以由当前执行的程序控制，该程序可以控制当前执行模式的使能信号。 挂起的中断条件和请求寄存器只能从特权操作模式访问。
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4.发明授权Apparatus and method for recovering from missing page faults in vector data processing operations 失效用于从向量数据处理操作中的错误页面错误中恢复的装置和方法
公开(公告)号：US5063497A
公开(公告)日：1991-11-05
申请号：US69372
申请日：1987-07-01
CPC分类号： G06F9/3865 , G06F12/08 , G06F15/8069 , G06F9/30036
摘要： In a data processing system employing virtual memory techniques and capable of performing a plurality of overlapping scalar and vector data processing operations, apparatus and method are provided to allow continuation of program execution after one or more vector load/store instructions, which refer to data values that are not currently in memory, receive page faults. At the occurrence of such a page fault, all instructions currently in execution are allowed to be completed, whereupon information summarizing the page fault condition is recorded in memory for use by the operating system software and a vector exception is generated. Operating system software responds to this exception, examines the fault information, causes the missing pages to be read into the main memory unit from the mass storage media, re-executes the exception producing vector instruction(s) and continues with the program execution.
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5.发明授权Apparatus and method for main memory unit protection using access and fault logic signals 失效使用访问和故障逻辑信号的主存储单元保护的装置和方法
公开(公告)号：US5317717A
公开(公告)日：1994-05-31
申请号：US932913
申请日：1992-08-20
IPC分类号： G06F12/14
CPC分类号： G06F12/1475
摘要： In a data processing system, apparatus and method for controlling the type of processing to which data signal groups can be subjected includes a page table entry format having a multiplicity of field positions for storing signals defining page access rights. In addition to the read/write access control, the signal group access rights can be determined by the current mode of operation of the data processing unit and the intended activity of the addressed instruction or data element (i.e., read, write or execute).
摘要翻译： 在数据处理系统中，用于控制数据信号组可以经受的处理类型的装置和方法包括具有多个字段位置的页表格格式，用于存储定义页访问权限的信号。 除了读/写访问控制之外，信号组访问权限可以由数据处理单元的当前操作模式和所寻址的指令或数据元素的预期活动（即，读，写或执行）来确定。
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公开(公告)号：US5278840A
公开(公告)日：1994-01-11
申请号：US005934
申请日：1993-01-15
CPC分类号： G06F9/30094 , G06F11/0721 , G06F11/0751 , G06F11/0772 , G06F11/3648 , G06F15/8053 , G06F9/30058
摘要： In a data processing system, an instruction is disclosed that generates a fault when a predetermined register position (e.g., the low or least significant bit position) has a predetermined logic signal (e.g., a logic `0` signal). This instruction provides a mechanism to determine when a Boolean value indicates a presence of a fault condition and provides a mechanism to generate the fault when present. For example, in arrays of memory locations that can be addressed by a program, this instruction can respond to the presence of an array address (or reference) that is outside the prescribed bounds of the array. When an invalid address is identified, a signal is entered in the low (i.e., least significant) bit position of a processor scalar register. The instruction repertoire includes a Fault on Low Bit Clear instruction that tests the contents of the scalar register low bit position, and when a logic `0` signal is found therein, an exception signal is generated and applied to the control program of the data processing system.
摘要翻译： 在数据处理系统中，公开了当预定的寄存器位置（例如，低或最低有效位位置）具有预定逻辑信号（例如，逻辑“0”信号）时产生故障的指令。 该指令提供了一种机制，用于确定布尔值何时指示故障状况的存在，并提供在存在时产生故障的机制。 例如，在可由程序寻址的存储器位置的阵列中，该指令可以响应在阵列的规定边界之外的阵列地址（或引用）的存在。 当识别出无效地址时，在处理器标量寄存器的低（即最低有效）位位置中输入信号。 该指令集包括一个低位清除指令，用于测试标量寄存器低位位置的内容，当发现逻辑“0”信号时，产生异常信号并将其应用于数据处理的控制程序 系统。
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7.发明授权Providing a data processor with a user-mode accessible mode of operations in which the processor performs processing operations without interruption 失效为数据处理器提供用户模式可访问操作模式，其中处理器不间断地执行处理操作
公开(公告)号：US5218712A
公开(公告)日：1993-06-08
申请号：US551040
申请日：1990-07-11
CPC分类号： G06F9/4812 , G06F15/8069 , G06F9/30145 , G06F9/30174 , G06F9/30189 , G06F9/455 , G06F9/45533 , G06F9/4843
摘要： In a data processing system employing microcode techniques, complex sequences of microinstructions can be initiated by application of a single macroinstruction. These complex sequences of microinstructions are typically noninterruptible and therefore the execution of a macroinstruction is atomic (i.e., executed as a single entity). Data processing systems that do not employ microcode typically have simpler macroinstruction sets that do not provide for a similar atomicity for complex instruction sequences. In order to obtain the same atomicity of instruction execution and to provide a nonmicrocoded data processing system with the capability to execute complex instruction sequences as an atomic operation, the nonmicrocoded data processing system is provided with a third mode, in addition to the (nonprivileged) user mode and the (privileged) kernel mode, of operation that permits the execution of instruction sequences with interrupting events disabled and certain functions and apparatus enabled to facilitate instruction sequence execution.
摘要翻译： 在采用微代码技术的数据处理系统中，微指令的复杂序列可以通过应用单个宏指令来启动。 这些微指令的复杂序列通常是不间断的，因此宏指令的执行是原子的（即，作为单个实体执行）。 不使用微代码的数据处理系统通常具有更简单的宏指令集，其不为复杂指令序列提供类似的原子性。 为了获得相同的指令执行原子性，并且提供具有执行复杂指令序列作为原子操作的能力的非微处理数据处理系统，除非非特定的（非特定的） 用户模式和允许执行中断事件的指令序列的操作的（特权）内核模式，并且启用某些功能和装置以便于指令序列执行。
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公开(公告)号：US4937824A
公开(公告)日：1990-06-26
申请号：US374601
申请日：1989-06-30
CPC分类号： G06F9/30094 , G06F9/30058 , G06F11/0721 , G06F11/0751 , G06F11/0772 , G06F11/362 , G06F15/8053
摘要： In a data processing system, an instruction is disclosed that generates a fault when a predetermined register position (e.g, the low or least significant bit position) has a predetermined logic signal (e.g., a logic `0` signal). This instruction provides a mechanism to determine when a Boolean value indicates a presence of a fault condition and provides a mechanism to generate the fault when present. For example, in arrays of memory locations that can be addressed by a program, this instruction can respond to the presence of an array address (or reference) that is outside the prescribed bounds of the array. When an invalid address is identified, a signal is entered in the low (i.e., least significant) bit position of a processor scalar register. The instruction repertoire includes a Fault on Low Bit Clear instruction that tests the contents of the scalar register low bit position, and when a logic `0` signal is found therein, an exception signal is generated and applied to the control program of the data processing system.
摘要翻译： 在数据处理系统中，公开了当预定的寄存器位置（例如，低或最低有效位位置）具有预定逻辑信号（例如，逻辑“0”信号）时产生故障的指令。 该指令提供了一种机制，用于确定布尔值何时指示故障状况的存在，并提供在存在时产生故障的机制。 例如，在可由程序寻址的存储器位置的阵列中，该指令可以响应在阵列的规定边界之外的阵列地址（或引用）的存在。 当识别出无效地址时，在处理器标量寄存器的低（即最低有效）位位置中输入信号。 该指令集包括一个低位清除指令，用于测试标量寄存器低位位置的内容，当发现逻辑“0”信号时，产生异常信号并将其应用于数据处理的控制程序 系统。
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公开(公告)号：US06243744B1
公开(公告)日：2001-06-05
申请号：US09085748
申请日：1998-05-26
申请人： William Snaman, Jr. , Wayne Cardoza
发明人： William Snaman, Jr. , Wayne Cardoza
IPC分类号： G06F15177
CPC分类号： G06F9/5061 , G06F2209/505
摘要： A technique for sharing a resource among a cluster of devices in a computer network. The technique involves generating a vote count that includes votes from voting devices attempting to form a cluster until the vote count reaches a quorum. The technique further involves, when the quorum is reached, selecting a most advanced generation indicator from among the voting devices, advancing the selected generation indicator and storing the advanced selected generation indicator in memory as a cluster generation indicator. Upon the advanced selected generation indicator being stored in memory, the cluster is formed and includes the voting devices. The technique further involves sharing a resource among the voting devices after the cluster is formed.
摘要翻译： 一种用于在计算机网络中的一组设备之间共享资源的技术。 该技术涉及产生一个投票数，其中包括投票设备尝试形成集群的投票，直到投票数达到法定人数。 该技术还涉及当达到法定人数时，从投票设备中选择最先进的生成指示符，推进所选择的生成指示符并将高级选择的生成指示符存储在存储器中作为集群生成指示符。 当高级选择的生成指示符存储在存储器中时，形成集群并且包括投票设备。 该技术还涉及在集群形成之后在投票设备之间共享资源。
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10.发明授权
公开(公告)号：US5008812A
公开(公告)日：1991-04-16
申请号：US170399
申请日：1988-03-18
申请人： Dileep P. Bhandarkar , Dave Cutler , Wayne Cardoza , Rich Witek , Dave Orbits
发明人： Dileep P. Bhandarkar , Dave Cutler , Wayne Cardoza , Rich Witek , Dave Orbits
CPC分类号： G06F9/462
摘要： The invention relates to a method and apparatus to minimize the time a data processing system spends on saving and restoring vector processor state data during a context switch. A context switch occurs when execution of an old process is suspended and execution of a current process is begun. The vector state data associated with the old process remains in the vector processor until the current process attempts to execute a vector instruction. When this occurs, the vector state data associated with the old process is saved and vector state data associated with the current process is restored, if the old process is not the same as the current process. If the old process is the same as the current process, there is no need to save and restore any vector state data.
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