公开(公告)号：US20090253238A1

公开(公告)日：2009-10-08

申请号：US12099726

申请日：2008-04-08

Applicant: Zhonghai SHI ,  David WU ,  Jingrong ZHOU ,  Ruigang LI

Inventor： Zhonghai SHI ,  David WU ,  Jingrong ZHOU ,  Ruigang LI

IPC: H01L21/8234

CPC classification number: H01L21/823437 ,  H01L21/823431 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785

Abstract: A fabrication process for a FinFET device is provided. The process begins by providing a semiconductor wafer having a layer of conductive material such as silicon. A whole-field arrangement of fins is then formed from the layer of conductive material. The whole-field arrangement of fins includes a plurality of conductive fins having a uniform pitch and a uniform fin thickness. Next, a cut mask is formed over the whole-field arrangement of fins. The cut mask selectively masks sections of the whole-field arrangement of fins with a layout that defines features for a plurality of FinFET devices. The cut mask is used to remove a portion of the whole-field arrangement of fins, the portion being unprotected by the cut mask. The resulting fin structures are used to complete the fabrication of the FinFET devices.

Abstract translation: 提供了一种用于FinFET器件的制造工艺。 该过程开始于提供具有诸如硅的导电材料层的半导体晶片。 然后由导电材料层形成翅片的全场排列。 翅片的全场布置包括具有均匀间距和均匀翅片厚度的多个导电翅片。 接下来，在翅片的整个场布置上形成切割掩模。 切割掩模选择性地屏蔽翅片的全场布置的部分，其布局限定了用于多个FinFET器件的特征。 切割掩模用于去除翅片的全场排列的一部分，该部分未被切割掩模保护。 所得到的翅片结构用于完成FinFET器件的制造。

公开(公告)号：US20090078991A1

公开(公告)日：2009-03-26

申请号：US11861051

申请日：2007-09-25

Applicant: Akif SULTAN ,  Mark MICHAEL ,  David WU ,  Donna Michael

Inventor： Akif SULTAN ,  Mark MICHAEL ,  David WU ,  Donna Michael

IPC: H01L29/78 ,  H01L21/762

CPC classification number: H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/7843

Abstract: A stress-enhanced semiconductor device is provided which includes a substrate having an inactive region and an active region, a first-type stress layer overlying at least a portion of the active region, and a second-type stress layer. The active region includes a first lateral edge which defines a first width of the active region, and a second lateral edge which defines a second width of the active region. The second-type stress layer is disposed adjacent the second lateral edge of the active region.

Abstract translation: 提供一种应力增强型半导体器件，其包括具有非活性区域和有源区域的衬底，覆盖有源区域的至少一部分的第一类型应力层和第二类型应力层。 有源区域包括限定有源区域的第一宽度的第一侧边缘和限定有源区域的第二宽度的第二侧边缘。 第二类应力层设置在活动区域​​的第二侧边缘附近。

公开(公告)号：US20110114217A1

公开(公告)日：2011-05-19

申请号：US12619949

申请日：2009-11-17

Applicant: David WU

Inventor： David WU

IPC: B21F45/00

CPC classification number: B21F35/00 ,  B21F3/02

Abstract: An abutting apparatus of spring configuration machine which has a machine platform includes a first and second axial transmission mechanisms and an abutting assembly. The first axial transmission mechanism includes a first actuator, a first lead screw and a first sliding seat screwed with the first lead screw. The second axial transmission mechanism includes a second actuator fixed to the first sliding seat, a second lead screw driven to rotate by the second actuator and a second sliding seat screwed with the second lead screw and linearly moved relatively to the first sliding seat. Via the first and second axial transmission mechanisms, the abutting assembly fixed to the second sliding seat can make a 2-D movement in vertical and horizontal directions relative to the machine platform, such that the degree of freedom to adjust the abutting assembly can be enhanced significantly.

Abstract translation: 具有机器平台的弹簧构造机的邻接装置包括第一和第二轴向传动机构和邻接组件。 第一轴向传动机构包括第一致动器，第一导螺杆和与第一导螺杆螺合的第一滑动座。 第二轴向传动机构包括固定到第一滑动座的第二致动器，被第二致动器驱动的第二导螺杆和与第二导螺杆螺合并且相对于第一滑动座线性移动的第二滑动座。 通过第一和第二轴向传动机构，固定到第二滑动座的抵接组件可相对于机器平台在垂直和水平方向上进行2-D运动，从而可以提高调节邻接组件的自由度 显着。

公开(公告)号：US20090081860A1

公开(公告)日：2009-03-26

申请号：US11861534

申请日：2007-09-26

Applicant: Jingrong ZHOU ,  Mark MICHAEL ,  Donna Michael ,  David WU ,  James F. BULLER ,  Akif SULTAN

Inventor： Jingrong ZHOU ,  Mark MICHAEL ,  Donna Michael ,  David WU ,  James F. BULLER ,  Akif SULTAN

IPC: H01L21/425

CPC classification number: H01L21/26513 ,  H01L21/26586 ,  H01L21/823807 ,  H01L29/1083

Abstract: The halo implant technique described herein employs a halo implant mask that creates a halo implant shadowing effect during halo dopant bombardment. A first transistor device structure and a second transistor device structure are formed on a wafer such that they are orthogonally oriented to each other. A common halo implant mask is created with features that prevent halo implantation of the diffusion region of the second transistor device structure during halo implantation of the diffusion region of the first transistor device structure, and with features that prevent halo implantation of the diffusion region of the first transistor device structure during halo implantation of the diffusion region of the second transistor device structure. The orthogonal orientation of the transistor device structures and the pattern of the halo implant mask obviates the need to create multiple implant masks to achieve different threshold voltages for the transistor device structures.

Abstract translation: 本文描述的光晕植入技术采用在光晕掺杂剂轰击期间产生晕轮植入物阴影效应的光晕注入掩模。 第一晶体管器件结构和第二晶体管器件结构形成在晶片上，使得它们彼此正交地取向。 创建了常见的光晕注入掩模，其特征在于，在第一晶体管器件结构的扩散区域的晕圈注入期间防止第二晶体管器件结构的扩散区域的光晕注入，并且具有防止第 在第二晶体管器件结构的扩散区的晕圈注入期间的第一晶体管器件结构。 晶体管器件结构的正交取向和光晕注入掩模的图案消除了创建多个注入掩模以实现晶体管器件结构的不同阈值电压的需要。

公开(公告)号：US20080296682A1

公开(公告)日：2008-12-04

申请号：US11755930

申请日：2007-05-31

Applicant: Jianhong ZHU ,  Jinrong ZHOU ,  David WU ,  James F. BULLER

Inventor： Jianhong ZHU ,  Jinrong ZHOU ,  David WU ,  James F. BULLER

IPC: H01L29/786 ,  H01L21/336

CPC classification number: H01L21/84 ,  H01L21/76895 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823475 ,  H01L27/1203 ,  H01L29/7843

Abstract: MOS structures with remote contacts and methods for fabricating such MOS structures are provided. In one embodiment, a method for fabricating an MOS structure comprises providing a semiconductor layer that is at least partially surrounded by an isolation region and that has an impurity-doped first portion. First and second MOS transistors are formed on and within the first portion. The transistors are substantially parallel and define a space therebetween. An insulating material is deposited overlying the first portion of the semiconductor layer and at least a portion of the isolation region. A contact is formed through the insulating material outside the space such that the contact is in electrical communication with the transistors.

Abstract translation: 提供了具有远程触点的MOS结构和用于制造这种MOS结构的方法。 在一个实施例中，一种用于制造MOS结构的方法包括提供半导体层，该半导体层至少部分地被隔离区包围，并且具有杂质掺杂的第一部分。 第一和第二MOS晶体管形成在第一部分内部和第一部分内。 晶体管基本上平行并且在它们之间限定了一个空间。 沉积覆盖半导体层的第一部分和隔离区域的至少一部分的绝缘材料。 通过空间外部的绝缘材料形成触点，使得触点与晶体管电连通。

公开(公告)号：US20080308879A1

公开(公告)日：2008-12-18

申请号：US11762133

申请日：2007-06-13

Applicant: Jianhong ZHU ,  Fred HAUSE ,  David WU

Inventor： Jianhong ZHU ,  Fred HAUSE ,  David WU

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L21/28518 ,  H01L21/28247 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/7833

Abstract: MOS structures with contact projections for lower contact resistance and methods for fabricating such MOS structures have been provided. In an embodiment, a method comprises providing a semiconductor substrate, fabricating a gate stack on the substrate, and forming a contact projection on the substrate. Ions of a conductivity-determining type are implanted within the substrate using the gate stack as an ion implantation mask to form impurity-doped regions within the substrate. A metal silicide layer is formed on the contact projection and a contact is formed to the metal silicide layer. The contact is in electrical communication with the impurity-doped regions via the contact projection.

Abstract translation: 已经提供了具有用于较低接触电阻的接触突起的MOS结构以及用于制造这种MOS结构的方法。 在一个实施例中，一种方法包括提供半导体衬底，在衬底上制造栅极堆叠，以及在衬底上形成接触突起。 使用栅极堆叠作为离子注入掩模将电导率确定类型的离子注入到衬底内，以在衬底内形成杂质掺杂区域。 在接触突起上形成金属硅化物层，并且与金属硅化物层形成接触。 触点通过接触突起与杂质掺杂区电连通。

公开(公告)号：US20120070987A1

公开(公告)日：2012-03-22

申请号：US13305449

申请日：2011-11-28

Applicant: Zhonghai SHI ,  David WU ,  Mark MICHAEL ,  Donna Michael

Inventor： Zhonghai SHI ,  David WU ,  Mark MICHAEL ,  Donna Michael

IPC: H01L21/768

CPC classification number: H01L29/41733 ,  H01L21/28518 ,  H01L21/76897 ,  H01L23/485 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78654 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices having improved contact resistance and methods for fabricating such semiconductor devices are provided. These semiconductor devices include a semiconductor device structure and a contact. The contact is electrically and physically coupled to the semiconductor device structure at both a surface portion and a sidewall portion of the semiconductor device structure.

Abstract translation: 提供了具有改善的接触电阻的半导体器件和制造这种半导体器件的方法。 这些半导体器件包括半导体器件结构和接触。 在半导体器件结构的表面部分和侧壁部分处，触点电耦合到半导体器件结构。

公开(公告)号：US20090081837A1

公开(公告)日：2009-03-26

申请号：US11861492

申请日：2007-09-26

Applicant: Zhonghai SHI ,  Mark MICHAEL ,  David WU ,  James F. BULLER ,  Jingrong ZHOU ,  Akif SULTAN ,  Donna Michael

Inventor： Zhonghai SHI ,  Mark MICHAEL ,  David WU ,  James F. BULLER ,  Jingrong ZHOU ,  Akif SULTAN ,  Donna Michael

IPC: H01L21/8238

CPC classification number: H01L21/823807 ,  H01L29/78 ,  H01L29/7843

Abstract: The techniques and technologies described herein relate to the automatic creation of photoresist masks for stress liners used with semiconductor based transistor devices. The stress liner masks are generated with automated design tools that leverage layout data corresponding to features, devices, and structures on the wafer. A resulting stress liner mask (and wafers fabricated using the stress liner mask) defines a stress liner coverage area that extends beyond the boundary of the transistor area and into a stress insensitive area of the wafer. The extended stress liner further enhances performance of the respective transistor by providing additional compressive/tensile stress.

Abstract translation: 本文所述的技术和技术涉及自动创建与半导体基晶体管器件一起使用的应力衬垫的光致抗蚀剂掩模。 应力衬垫掩模是利用自动设计工具生成的，其利用与晶片上的特征，器件和结构对应的布局数据。 产生的应力衬垫掩模（以及使用应力衬垫掩模制造的晶片）限定了延伸超出晶体管区域的边界并进入晶片的应力不敏感区域的应力衬垫覆盖区域。 延伸的应力衬垫通过提供额外的压缩/拉伸应力来进一步提高相应晶体管的性能。