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公开(公告)号：US20050024094A1
公开(公告)日：2005-02-03
申请号：US10830664
申请日：2004-04-23
申请人： Declan Dalton , Lawrence DeVito , Mark Ferriss , Paul Murray
发明人： Declan Dalton , Lawrence DeVito , Mark Ferriss , Paul Murray
CPC分类号： H03D13/004 , H03L7/087 , H03L7/0891 , H03L7/091 , H03L7/10 , H04L7/033
摘要： A rotational frequency detector system including a rotational frequency detector responsive to a data signal and a clock signal. The rotational frequency detector is configured to compare the frequency of the clock signal to the frequency of the data signal to define frequency up and frequency down signals that adjust the frequency of the clock signal to be equal to the frequency of the data signal. A step control system is responsive to the rotational frequency detector and a step clock signal and is configured to define predetermined pulse widths for the frequency up and frequency down signals.
摘要翻译： 一种旋转频率检测器系统，包括响应数据信号和时钟信号的旋转频率检测器。 旋转频率检测器被配置为将时钟信号的频率与数据信号的频率进行比较，以定义将时钟信号的频率调整为等于数据信号的频率的上变频和下变频信号。 步进控制系统响应于旋转频率检测器和步进时钟信号，并且被配置为为上变频信号和降频信号定义预定的脉冲宽度。
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公开(公告)号：US20050027763A1
公开(公告)日：2005-02-03
申请号：US10832187
申请日：2004-04-26
申请人： Declan Dalton , Lawrence DeVito , Mark Ferriss , Paul Murray
发明人： Declan Dalton , Lawrence DeVito , Mark Ferriss , Paul Murray
摘要： A harmonic detector including a pattern detector circuit responsive to a clock signal and a data signal configured to detect a target bit pattern from said data signal, and a time-out circuit responsive to said pattern detector circuit configured to detect the absence of said target bit pattern during a predetermined time-out parameter for indicating when said clock signal exceeds said data signal by a factor of two or more.
摘要翻译： 一种谐波检测器，包括响应于时钟信号的模式检测器电路和被配置为从所述数据信号检测目标位模式的数据信号，以及响应于所述模式检测器电路的超时电路，被配置为检测所述目标位的不存在 在预定的超时参数期间，用于指示何时所述时钟信号超过所述数据信号2倍或更多倍。
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公开(公告)号：US20050057290A1
公开(公告)日：2005-03-17
申请号：US10893198
申请日：2004-07-16
CPC分类号： H03D13/003
摘要： An improved coarse frequency detector includes a first storage device responsive to a data signal and a sub-multiple of a clock signal for detecting a first transition in the data signal during a predetermined state of the sub-multiple of the clock signal and generating an intermediate signal, and a second storage device responsive to the data signal and the intermediate signal for detecting a second transition in the data signal having the same polarity as the first transition during the predetermined state of the sub-multiple of the clock signal and generating an up-pulse.
摘要翻译： 改进的粗略频率检测器包括响应于数据信号的第一存储装置和用于在时钟信号的子倍数的预定状态期间检测数据信号中的第一转换的时钟信号的子倍数，并且产生中间 信号，以及响应于数据信号和中间信号的第二存储装置，用于检测在时钟信号的子倍数的预定状态期间具有与第一转换相同极性的数据信号中的第二转换，并产生上升 -脉冲。
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公开(公告)号：US07285994B2
公开(公告)日：2007-10-23
申请号：US10830664
申请日：2004-04-23
IPC分类号： H03L7/06
CPC分类号： H03D13/004 , H03L7/087 , H03L7/0891 , H03L7/091 , H03L7/10 , H04L7/033
摘要： A rotational frequency detector system including a rotational frequency detector responsive to a data signal and a clock signal. The rotational frequency detector is configured to compare the frequency of the clock signal to the frequency of the data signal to define frequency up and frequency down signals that adjust the frequency of the clock signal to be equal to the frequency of the data signal. A step control system is responsive to the rotational frequency detector and a step clock signal and is configured to define predetermined pulse widths for the frequency up and frequency down signals.
摘要翻译： 一种旋转频率检测器系统，包括响应数据信号和时钟信号的旋转频率检测器。 旋转频率检测器被配置为将时钟信号的频率与数据信号的频率进行比较，以定义将时钟信号的频率调整为等于数据信号的频率的上变频和下变频信号。 步进控制系统响应于旋转频率检测器和步进时钟信号，并且被配置为为上变频信号和降频信号定义预定的脉冲宽度。
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公开(公告)号：US07145398B2
公开(公告)日：2006-12-05
申请号：US10893198
申请日：2004-07-16
CPC分类号： H03D13/003
摘要： An improved coarse frequency detector includes a first storage device responsive to a data signal and a sub-multiple of a clock signal for detecting a first transition in the data signal during a predetermined state of the sub-multiple of the clock signal and generating an intermediate signal, and a second storage device responsive to the data signal and the intermediate signal for detecting a second transition in the data signal having the same polarity as the first transition during the predetermined state of the sub-multiple of the clock signal and generating an up-pulse.
摘要翻译： 改进的粗略频率检测器包括响应于数据信号的第一存储装置和用于在时钟信号的子倍数的预定状态期间检测数据信号中的第一转换的时钟信号的子倍数，并且产生中间 信号，以及响应于数据信号和中间信号的第二存储装置，用于检测在时钟信号的子倍数的预定状态期间具有与第一转换相同极性的数据信号中的第二转换，并产生上升 -脉冲。
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公开(公告)号：US08570079B2
公开(公告)日：2013-10-29
申请号：US13226557
申请日：2011-09-07
IPC分类号： H03L7/06
CPC分类号： H03L7/0893 , H03L2207/06
摘要： There is provided a method for reducing lock time in a phase locked loop. The method includes detecting a saturation condition on a path within the phase locked loop. The method further includes temporarily applying saturation compensation along the path when the saturation condition is detected.
摘要翻译： 提供了一种减少锁相环锁定时间的方法。 该方法包括检测锁相环内的路径上的饱和状态。 该方法还包括当检测到饱和条件时，沿路径暂时施加饱和补偿。
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公开(公告)号：US09157950B2
公开(公告)日：2015-10-13
申请号：US13088949
申请日：2011-04-18
申请人： Mark Ferriss , Arun S. Natarajan , Benjamin D. Parker , Alexander V. Rylyakov , Jose A. Tierno , Soner Yaldiz
发明人： Mark Ferriss , Arun S. Natarajan , Benjamin D. Parker , Alexander V. Rylyakov , Jose A. Tierno , Soner Yaldiz
CPC分类号： H03L7/085 , G01R31/2824 , H03L7/093 , H03L7/1075 , H03L7/1077 , H03L7/18 , H03L2207/06
摘要： A method and system are disclosed for measuring a specified parameter in a phase-locked loop frequency synthesizer (PLL). In one embodiment, the method comprises introducing multiple phase errors in the PLL, measuring a specified aspect of the introduced phase errors, and determining a value for the specified parameter using the measured aspects of the introduced phase errors. In one embodiment, the phase errors are introduced repetitively in the PLL, and these phase errors produce a modified phase difference between the reference signal and the feedback signal in the PPL. In one embodiment, crossover times, when this modified phase difference crosses over a preset value, are determined, and these crossover times are used to determine the value for the specified parameter. In an embodiment, the parameter is calculated as a mathematical function of the crossover times. The parameter may be, for example, the bandwidth of the PLL.
摘要翻译： 公开了用于测量锁相环频率合成器（PLL）中的指定参数的方法和系统。 在一个实施例中，该方法包括在PLL中引入多个相位误差，测量所引入的相位误差的特定方面，以及使用引入的相位误差的测量方面来确定所述指定参数的值。 在一个实施例中，在PLL中重复地引入相位误差，并且这些相位误差在PPL中产生参考信号和反馈信号之间的修正的相位差。 在一个实施例中，当修改的相位差超过预设值时，交叉时间被确定，并且这些交叉时间被用于确定指定参数的值。 在一个实施例中，该参数被计算为交叉时间的数学函数。 该参数可以是例如PLL的带宽。
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公开(公告)号：US20120262149A1
公开(公告)日：2012-10-18
申请号：US13088949
申请日：2011-04-18
申请人： Mark Ferriss , Arun S. Natarajan , Benjamin D. Parker , Alexander V. Rylyakov , Jose A. Tierno , Soner Yaldiz
发明人： Mark Ferriss , Arun S. Natarajan , Benjamin D. Parker , Alexander V. Rylyakov , Jose A. Tierno , Soner Yaldiz
IPC分类号： G01R25/00
CPC分类号： H03L7/085 , G01R31/2824 , H03L7/093 , H03L7/1075 , H03L7/1077 , H03L7/18 , H03L2207/06
摘要： A method and system are disclosed for measuring a specified parameter in a phase-locked loop frequency synthesizer (PLL). In one embodiment, the method comprises introducing multiple phase errors in the PLL, measuring a specified aspect of the introduced phase errors, and determining a value for the specified parameter using the measured aspects of the introduced phase errors. In one embodiment, the phase errors are introduced repetitively in the PLL, and these phase errors produce a modified phase difference between the reference signal and the feedback signal in the PPL. In one embodiment, crossover times, when this modified phase difference crosses over a preset value, are determined, and these crossover times are used to determine the value for the specified parameter. In an embodiment, the parameter is calculated as a mathematical function of the crossover times. The parameter may be, for example, the bandwidth of the PLL.
摘要翻译： 公开了用于测量锁相环频率合成器（PLL）中的指定参数的方法和系统。 在一个实施例中，该方法包括在PLL中引入多个相位误差，测量所引入的相位误差的特定方面，以及使用引入的相位误差的测量方面来确定所述指定参数的值。 在一个实施例中，在PLL中重复地引入相位误差，并且这些相位误差在PPL中产生参考信号和反馈信号之间的修正的相位差。 在一个实施例中，当修改的相位差超过预设值时，交叉时间被确定，并且这些交叉时间被用于确定指定参数的值。 在一个实施例中，该参数被计算为交叉时间的数学函数。 该参数可以是例如PLL的带宽。
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公开(公告)号：US07512202B2
公开(公告)日：2009-03-31
申请号：US10832187
申请日：2004-04-26
IPC分类号： H04L7/00
摘要： A harmonic detector including a pattern detector circuit responsive to a clock signal and a data signal configured to detect a target bit pattern from said data signal, and a time-out circuit responsive to said pattern detector circuit configured to detect the absence of said target bit pattern during a predetermined time-out parameter for indicating when said clock signal exceeds said data signal by a factor of two or more.
摘要翻译： 一种谐波检测器，包括响应于时钟信号的模式检测器电路和被配置为从所述数据信号检测目标位模式的数据信号，以及响应于所述模式检测器电路的超时电路，被配置为检测所述目标位的不存在 在预定的超时参数期间，用于指示何时所述时钟信号超过所述数据信号2倍或更多倍。
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