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    Semiconductor device fabrication process
    1.
    发明授权
    Semiconductor device fabrication process 失效
    半导体器件制造工艺

    公开(公告)号：US4512076A

    公开(公告)日：1985-04-23

    申请号：US450900

    申请日：1982-12-20

    申请人： Deepak Mehrotra ,  Gerard J. Shaw ,  Jok Y. Go ,  Rajni Kant

    发明人： Deepak Mehrotra ,  Gerard J. Shaw ,  Jok Y. Go ,  Rajni Kant

    IPC分类号： H01L27/082 ,  H01L21/033 ,  H01L21/285 ,  H01L21/331 ,  H01L21/768 ,  H01L21/8222 ,  H01L27/06 ,  H01L29/47 ,  H01L29/73 ,  H01L29/872 ,  H01L21/86

    CPC分类号： H01L21/768 ,  H01L21/033 ,  H01L21/28525

    摘要： A semiconductor device fabrication process is provided wherein a first window is formed in a first silicon dioxide layer which is disposed over the surface of a silicon layer to expose a first portion of the silicon layer. A doped region is formed in the first portion of a silicon layer exposed by the first window. A second layer of silicon dioxide is deposited over the surface of the first, previously formed, silicon dioxide layer and over the first portion of the silicon layer exposed by the first window. A second window is formed through the first and second silicon dioxide layers to expose a second, different portion of the surface of the silicon layer. A layer of silicon nitride is disposed over the second layer of silicon dioxide and through the second formed window onto the portion of the silicon layer exposed by such second formed window. The surface of the structure is then masked with windows being formed in such mask over the first and second previously exposed portions of the silicon layer. An etchant is brought into contact with portions of the silicon nitride layer exposed by the windows formed in the mask to selectively remove the portions of the silicon nitride layer exposed by such windows and to thereby expose the portion of the second silicon dioxide layer disposed over the first exposed portion of the silicon layer and the second exposed portion of the silicon layer. A Schottky contact metal is deposited over the surface of the structure and onto the second exposed portion of the silicon layer to form a Schottky contact region. The portion of the second silicon dioxide layer disposed over the first exposed portion of the silicon layer is then selectively removed with a chemical etchant to expose a portion of the previously formed doped region.

    摘要翻译： 提供了半导体器件制造方法，其中第一窗口形成在第一二氧化硅层中，第一二氧化硅层设置在硅层的表面上以暴露硅层的第一部分。 在由第一窗露出的硅层的第一部分中形成掺杂区域。 第二层二氧化硅沉积在第一先前形成的二氧化硅层的表面上，并且在由第一窗露出的硅层的第一部分之上。 通过第一和第二二氧化硅层形成第二窗口以暴露硅层表面的第二不同部分。 氮化硅层设置在第二二氧化硅层上并通过第二形成的窗口放置在由这种第二成形窗露出的硅层的部分上。 然后在硅层的第一和第二先前暴露部分上的这种掩模中形成窗口来掩蔽该结构的表面。 使蚀刻剂与形成在掩模中的窗口暴露的氮化硅层的部分接触，以选择性地去除由这种窗口暴露的氮化硅层的部分，从而暴露位于该掩模上的第二二氧化硅层的部分 硅层的第一暴露部分和硅层的第二暴露部分。 将肖特基接触金属沉积在结构的表面上并沉积到硅层的第二暴露部分上以形成肖特基接触区域。 然后用化学蚀刻剂选择性地去除设置在硅层的第一暴露部分上的第二二氧化硅层的部分，以暴露先前形成的掺杂区域的一部分。

    Configurable logic gate array
    2.
    发明授权
    Configurable logic gate array 失效
    可配置逻辑门阵列

    公开(公告)号：US4527115A

    公开(公告)日：1985-07-02

    申请号：US452169

    申请日：1982-12-22

    申请人： Deepak Mehrotra ,  Rajni Kant ,  Kishor M. Patel

    发明人： Deepak Mehrotra ,  Rajni Kant ,  Kishor M. Patel

    IPC分类号： G01R31/28 ,  G01R31/317 ,  G01R31/3185 ,  H03K19/177 ,  G01R15/12

    CPC分类号： G01R31/318516

    摘要： A configurable logic gate array having an array of logic gates adapted for selective electrical interconnection to provide a predetermined logic function on a plurality of input logic signals fed to the configured gate array and produce such predetermined logic function as an output signal at an array output terminal. An output buffer circuit is coupled between the output of an interconnected gate and the array output terminal. A parametric testing circuit is responsive to a control signal for electrically coupling, during a normal operating mode, the output of the interconnected gate to the array output terminal, or, during a parameter testing mode, a logic signal source for producing "high" and "low" logic output voltages representative of the logic output voltage produced by the logic gates in response to the logic input signals.With such arrangement, there is a reduction in the test program development time since bringing the output to the desired state (high or low) be sequencing through function testing to achieve the desired state on the desired pin (an error prone, time consuming process requiring full understanding of the logic implemented and rationale applied by customer in generating test vectors) is eliminated. Further, with such an arrangement, parametric testing of the output signals by the gates in the array is performed by merely driving each output buffer circuit to "high" or "low" logic states thereby reducing parametric testing time of the gate array after the logic gates have been selectively electrically interconnected to provide the desired predetermined logic function.

    摘要翻译： 一种可配置的逻辑门阵列，其具有适于选择性电互连的逻辑门阵列，以向馈送到所配置的门阵列的多个输入逻辑信号提供预定的逻辑功能，并产生诸如阵列输出端的输出信号的预定逻辑功能 。 输出缓冲电路耦合在互连栅极的输出端与阵列输出端子之间。 参数测试电路响应于控制信号，用于在正常操作模式期间将互连栅极的输出电耦合到阵列输出端子，或者在参数测试模式期间，用于产生“高”和 代表由逻辑门响应逻辑输入信号产生的逻辑输出电压的“低”逻辑输出电压。 通过这种布置，测试程序开发时间有所减少，因为将输出输出到期望状态（高或低）是通过功能测试进行排序，以在期望的引脚上实现所需的状态（需要错误的，耗时的过程 全面了解客户在生成测试向量中应用的逻辑实现和理论基础）。 此外，通过这样的布置，通过仅将驱动每个输出缓冲器电路为“高”或“低”逻辑状态来执行阵列中的栅极的输出信号的参数测试，从而减少逻辑后的门阵列的参数测试时间 门已经选择性地电互连以提供期望的预定逻辑功能。

    Integrated tunable high efficiency power amplifier
    5.
    发明授权
    Integrated tunable high efficiency power amplifier 有权
    集成可调高效率功率放大器

    公开(公告)号：US06232841B1

    公开(公告)日：2001-05-15

    申请号：US09346097

    申请日：1999-07-01

    申请人： James L. Bartlett ,  Mau Chung F. Chang ,  Henry O. Marcy, 5th ,  Kenneth D. Pedrotti ,  David R. Pehlke ,  Charles W. Seabury ,  Jun J. Yao ,  Deepak Mehrotra ,  J. L. Julian Tham

    发明人： James L. Bartlett ,  Mau Chung F. Chang ,  Henry O. Marcy, 5th ,  Kenneth D. Pedrotti ,  David R. Pehlke ,  Charles W. Seabury ,  Jun J. Yao ,  Deepak Mehrotra ,  J. L. Julian Tham

    IPC分类号： H03F304

    CPC分类号： H03F3/2176 ,  H01H59/0009

    摘要： Power amplifiers having reactive networks (such as classes C, C-E, E and F) employ tunable reactive devices in their reactive networks, with the reactive devices respective reactance values capable of being adjusted by means of respective control signals. The tunable reactive devices are made from micro-electromechanical (MEM) devices capable of being integrated with the control circuitry needed to produce the control signals and other amplifier components on a common substrate. The reactive components have high Q values across their adjustment range, enabling the amplifier to produce an output with a low harmonic content over a wide range of input signal frequencies, and a frequency agile, high quality output. The invention can be realized on a number of foundry technologies.

    摘要翻译： 具有无功网络（例如类C，C-E，E和F）的功率放大器在其无功网络中采用可调谐无功装置，其中无功装置可以通过相应的控制信号来调整各自的电抗值。 可调谐无功装置由能够与在公共基板上产生控制信号和其它放大器部件所需的控制电路集成的微机电（MEM）器件制成。 无功分量在其调节范围内具有高Q值，使得放大器能够在宽范围的输入信号频率以及频率灵敏，高质量输出下产生具有低谐波含量的输出。 本发明可以通过多种铸造技术实现。

    Integrated variable gain power amplifier and method
    6.
    发明授权
    Integrated variable gain power amplifier and method 失效
    集成可变增益功率放大器及方法

    公开(公告)号：US5834975A

    公开(公告)日：1998-11-10

    申请号：US815694

    申请日：1997-03-12

    申请人： James L. Bartlett ,  Mau Chung F. Chang ,  J. Aiden Higgins ,  Henry O. Marcy, 5th ,  Deepak Mehrotra ,  Kenneth D. Pedrotti ,  David R. Pehlke ,  Charles W. Seabury ,  J. L. Julian Tham ,  Jun J. Yao

    发明人： James L. Bartlett ,  Mau Chung F. Chang ,  J. Aiden Higgins ,  Henry O. Marcy, 5th ,  Deepak Mehrotra ,  Kenneth D. Pedrotti ,  David R. Pehlke ,  Charles W. Seabury ,  J. L. Julian Tham ,  Jun J. Yao

    IPC分类号： H03G1/00 ,  H03G3/30 ,  H03F3/68

    CPC分类号： H03F3/72 ,  H03F1/0277 ,  H03F3/211 ,  H03G1/0088

    摘要： An integrated, variable gain microwave frequency power amplifier comprises a number of individual amplifier stages which contain microwave frequency active devices. Each stage is fed with a common input signal, and the individual stage outputs are connected to respective micro-electromechanical (MEM) switches which, when closed, connect the individual outputs together to form the power amplifier's output. The power amplifier's gain is determined by the number of outputs connected together. The preferred switch provides low insertion loss and excellent electrical isolation, enabling a number of amplifier stages to be efficiently interconnected to provide a wide dynamic range power amplifier. The switches are preferably integrated on a common substrate with the active devices, eliminating the need for wire bonds and reducing parasitic capacitances. A variable impedance network comprising a number of impedance matching networks selected using MEM switches can be connected to and integrated with a variable gain power amplifier to provide impedance matching that is appropriate for each of the power amplifier's possible output power levels.

    摘要翻译： 集成的可变增益微波频率功率放大器包括多个单独的放大器级，其包含微波频率有源器件。 每个级馈入一个公共输入信号，并且各个级输出连接到相应的微机电（MEM）开关，当关闭时，各个输出端连接在一起形成功率放大器的输出。 功率放大器的增益取决于连接在一起的输出数量。 优选的开关提供低插入损耗和优异的电隔离，使得能够高效地互连多个放大器级，以提供宽动态范围功率放大器。 这些开关优选地与有源器件集成在公共衬底上，消除了对引线键合的需要并降低寄生电容。 包括使用MEM开关选择的多个阻抗匹配网络的可变阻抗网络可以连接到可变增益功率放大器并与可变增益功率放大器集成，以提供适合于每个功率放大器的可能输出功率电平的阻抗匹配。

    Monolithically integrated switched capacitor bank using micro electro mechanical system (MEMS) technology
    8.
    发明授权
    Monolithically integrated switched capacitor bank using micro electro mechanical system (MEMS) technology 失效
    使用微机电系统（MEMS）技术的单片集成开关电容器组

    公开(公告)号：US5880921A

    公开(公告)日：1999-03-09

    申请号：US848116

    申请日：1997-04-28

    申请人： J.L. Julian Tham ,  James L. Bartlett ,  Mau Chung F. Chang ,  Henry O. Marcy, 5th ,  Deepak Mehrotra ,  Kenneth D. Pedrotti ,  David R. Pehlke ,  Charles W. Seabury ,  Jun J. Yao

    发明人： J.L. Julian Tham ,  James L. Bartlett ,  Mau Chung F. Chang ,  Henry O. Marcy, 5th ,  Deepak Mehrotra ,  Kenneth D. Pedrotti ,  David R. Pehlke ,  Charles W. Seabury ,  Jun J. Yao

    IPC分类号： H01H59/00 ,  H03B1/00 ,  H01G23/00

    CPC分类号： H01H59/0009 ,  H01G5/16 ,  H01H2001/0084 ,  H03B2201/0208 ,  H03B2201/0216 ,  H03B2201/025 ,  H03J2200/10

    摘要： A monolithically integrated switched capacitor bank using MEMS technology that is capable of handling GHz signal frequencies in both the RF and millimeter bands while maintaining precise digital selection of capacitor levels over a wide tuning range. Each MEMS switch includes a cantilever arm that is affixed to the substrate and extends over a ground line and a gapped signal line. An electrical contact is formed on the bottom of the cantilever arm positioned above and facing the gap in the signal line. A top electrode atop the cantilever arm forms a control capacitor structure above the ground line. A capacitor structure, preferably a MEMS capacitor suspended above the substrate at approximately the same height as the cantilever arm, is anchored to the substrate and connected in series with a MEMS switch. The MEMS switch is actuated by applying a voltage to the top electrode, which produces an electrostatic force that attracts the control capacitor structure toward the ground line, thereby causing the electrical contact to close the gap in the signal line and connect the MEMS capacitor structure between a pair of output terminals. The integrated MEMS switch-capacitor pairs have a large range between their on-state and off-state impedance, and thus exhibit superior isolation and insertion loss characteristics.

    摘要翻译： 使用MEMS技术的单片集成开关电容器组，其能够处理RF和毫米波段中的GHz信号频率，同时在宽调谐范围内保持电容器电平的精确数字选择。 每个MEMS开关包括悬臂，其固定在基板上并在接地线和间隙信号线上延伸。 在位于信号线上方并面向信号线的间隙的悬臂的底部上形成电接触。 在悬臂上方的顶部电极在地线上方形成控制电容器结构。 电容器结构，优选地悬置在基板上方的悬臂上方与悬臂大致相同高度的MEMS电容器被锚定到基板并与MEMS开关串联连接。 通过向顶部电极施加电压来致动MEMS开关，该电压产生吸引控制电容器结构朝向接地线的静电力，从而使电接触闭合信号线中的间隙，并将MEMS电容器结构 一对输出端子。 集成的MEMS开关电容器对在其导通状态和截止状态阻抗之间具有较大的范围，因此表现出优异的隔离和插入损耗特性。

    Reversible sheets and pillowcases
    9.
    发明申请
    Reversible sheets and pillowcases 审中-公开
    可逆的床单和枕套

    公开(公告)号：US20070028383A1

    公开(公告)日：2007-02-08

    申请号：US11498360

    申请日：2006-08-02

    申请人： Deepak Mehrotra

    发明人： Deepak Mehrotra

    IPC分类号： A47G9/02 ,  A47G9/00

    CPC分类号： A47G9/0238 ,  A47G9/0253

    摘要： A reversible bedding article such as a top sheet, a fitted sheet, or a pillowcase, comprises at least one single layer fabric sheet having a first face, a second face opposite the first face, a main piece, and one or more edge pieces, wherein a first design motif is applied to the first face and a second design motif is applied to the second face, and each face has a finished surface. The main piece and one or more edge pieces are joined by at least one seam to produce a bedding article presenting a finished appearance on either face of the article.

    摘要翻译： 一种可逆的床上用品，例如顶片，装饰片或枕套，包括至少一个单层织物片，其具有第一面，与第一面相对的第二面，主片和一个或多个边缘片， 其中将第一设计图案应用于所述第一面，并且将第二设计图案应用于所述第二面，并且每个面具有成品表面。 主片和一个或多个边缘片通过至少一个接缝连接以产生在制品的任一面上具有完成外观的床上用品。