Method for forming a bipolar emitter using doped SOG
    3.
    发明授权
    Method for forming a bipolar emitter using doped SOG 失效
    使用掺杂SOG形成双极型发射极的方法

    公开(公告)号:US5322805A

    公开(公告)日:1994-06-21

    申请号:US961973

    申请日:1992-10-16

    摘要: A method for forming a bipolar emitter using doped SOG which employs diffusion instead of implanting, and which produces a shallow, low-resistance emitter using a variety of dopants besides boron and phosphorus. A layer of doped SOG is spun over a predefined base region. Portions of the SOG layer are defined for removal and removed, leaving the collector and emitter contact areas exposed. The SOG layer is densified and the dopants are driven into the base to form the emitter.

    摘要翻译: 使用掺杂SOG形成双极型发射体的方法,其使用扩散而不是植入,并且使用除硼和磷之外的各种掺杂剂产生浅的低电阻发射体。 在预定义的碱性区域上旋转一层掺杂的SOG。 SOG层的部分被限定为去除和去除,使集电极和发射极接触区域暴露。 SOG层被致密化并且掺杂剂被驱动到基底中以形成发射极。

    Selective sidewall diffusion process using doped SOG
    7.
    发明授权
    Selective sidewall diffusion process using doped SOG 失效
    使用掺杂SOG的选择性侧壁扩散过程

    公开(公告)号:US5308790A

    公开(公告)日:1994-05-03

    申请号:US961967

    申请日:1992-10-16

    摘要: A selective sidewall diffusion process using doped SOG. A substrate is processed to form raised portions or pedestals, having sidewalls, and trenches. A first layer, either a doped SOG layer or undoped oxide layer, may be deposited onto the substrate adjacent the sidewalls. The first layer is densified. A second layer may be deposited on the first layer. The second layer is a doped SOG layer. The second layer is densified and the dopant is driven into the sidewalls to form shallow junctions.

    摘要翻译: 使用掺杂SOG的选择性侧壁扩散工艺。 处理衬底以形成具有侧壁和沟槽的凸起部分或基座。 掺杂的SOG层或未掺杂的氧化物层的第一层可以沉积在邻近侧壁的衬底上。 第一层被致密化。 第二层可以沉积在第一层上。 第二层是掺杂的SOG层。 第二层被致密化并且掺杂剂被驱动到侧壁中以形成浅结。

    Method for composing a dielectric layer within an interconnect structure of a multilayer semiconductor device
    10.
    发明授权
    Method for composing a dielectric layer within an interconnect structure of a multilayer semiconductor device 失效
    在多层半导体器件的互连结构内构成电介质层的方法

    公开(公告)号:US06806162B1

    公开(公告)日:2004-10-19

    申请号:US10459072

    申请日:2003-06-11

    IPC分类号: H01L2176

    摘要: A method for composing a dielectric layer within an interconnect structure of a multilayer semiconductor device is disclosed. A layer of silica precursor material is first deposited on a silicon substrate. Without affecting its structure and porosity, the layer of silica precursor material is then dried; and the layer of silica precursor material becomes porous silica film. Subsequently, a protective layer, such as parylene, is deposited on top of the dried porous silica film. The thickness of the protective layer should be greater than the peak-valley planarization requirements of the silicon substrate surface. As a result, a composite porous silica film, which services as a dielectric layer within an interconnect structure, is formed. This composite porous silica film has a relatively low dielectric constant and is able to withstand damage from a standard CMP procedure.

    摘要翻译: 公开了一种用于构成多层半导体器件的互连结构内的电介质层的方法。 首先在硅衬底上沉积二氧化硅前体材料层。 然后不影响其结构和孔隙率,然后干燥二氧化硅前体材料层; 并且二氧化硅前体材料层变成多孔二氧化硅膜。 随后,在干燥的多孔二氧化硅膜的顶部上沉积保护层,例如聚对二甲苯。 保护层的厚度应大于硅衬底表面的峰 - 谷平面化要求。 结果,形成了用作互连结构内的介电层的复合多孔二氧化硅膜。 该复合多孔二氧化硅膜具有相对较低的介电常数,能够承受来自标准CMP工艺的损伤。