公开(公告)号：US06639829B2

公开(公告)日：2003-10-28

申请号：US09922471

申请日：2001-08-03

申请人： Dietmar Gogl ,  Helmut Kandolf ,  Stefan Lammers

发明人： Dietmar Gogl ,  Helmut Kandolf ,  Stefan Lammers

IPC分类号： G11C1100

CPC分类号： G11C5/063 ,  G11C11/15 ,  G11C11/16

摘要： A configuration and method for low-loss writing of an MRAM includes setting voltages at bit lines and word lines such that the voltage across the memory cells between a selected word/bit line and the individual bit line/word lines is minimal. A voltage drop occurs on a selected word/bit line connected to a particular memory cell when writing into the memory cell and voltages at the bit/word lines are set to minimize a cell voltage across the memory cells between a selected word/bit line and individual bit/word lines. A voltage drop occurs on a selected word/bit line connected to a particular memory cell when writing into the particular cell, and, when a voltage V1 and a voltage V2

公开(公告)号：US06577528B2

公开(公告)日：2003-06-10

申请号：US10023155

申请日：2001-12-17

申请人： Dietmar Gogl ,  Helmut Kandolf ,  Heinz Hönigschmid

发明人： Dietmar Gogl ,  Helmut Kandolf ,  Heinz Hönigschmid

IPC分类号： G11C1100

CPC分类号： G11C8/12 ,  G11C11/15

摘要： A circuit configuration for controlling write operations and read operations in an MRAM memory configuration includes selection transistors grouped in sections of equal numbers of the selection transistors. The selection transistors of each of the sections are jointly connected, at the ends of the bit lines, to a respective interacting pair of read/write amplifiers via those electrode terminals of the selection transistors that are not connected to the bit lines. The read/write amplifiers are controlled such that if a write signal is fed thereto, write currents for writing a logic “1” or “0” flow in a first direction or a second direction in all of the bit lines selected by a corresponding column select signal and, if a read signal is fed in, a logic state stored in one of the magnetoresistive memory cells can be read out.

公开(公告)号：US20060152970A1

公开(公告)日：2006-07-13

申请号：US10905585

申请日：2005-01-12

申请人： John DeBrosse ,  Dietmar Gogl ,  Stefan Lammers ,  Hans Viehmann

发明人： John DeBrosse ,  Dietmar Gogl ,  Stefan Lammers ,  Hans Viehmann

IPC分类号： G11C11/14

CPC分类号： G11C11/16 ,  G11C29/02 ,  G11C29/026 ,  G11C29/028 ,  G11C2029/1204

摘要： A calibrated magnetic random access memory (MRAM) current sense amplifier includes a first plurality of trim transistors selectively configured in parallel with a first load device, the first load device associated with a data side of the sense amplifier. A second plurality of trim transistors is selectively configured in parallel with a second load device, the second load device associated with a reference side of the sense amplifier. The first and said second plurality of trim transistors are individually activated so as to compensate for device mismatch with respect to the data and reference sides of the sense amplifier.

摘要翻译： 校准磁性随机存取存储器（MRAM）电流检测放大器包括与第一负载装置并联的第一多个调整晶体管，第一负载装置与读出放大器的数据侧相关联。 与第二负载装置并联地选择性地配置第二组微调晶体管，第二负载装置与感测放大器的参考侧相关联。 单独激活第一和第二多个微调晶体管，以补偿相对于读出放大器的数据和参考侧的器件失配。

公开(公告)号：US06577527B2

公开(公告)日：2003-06-10

申请号：US09999324

申请日：2001-10-31

申请人： Martin Freitag ,  Stefan Lammers ,  Dietmar Gogl ,  Thomas Roehr

发明人： Martin Freitag ,  Stefan Lammers ,  Dietmar Gogl ,  Thomas Roehr

IPC分类号： G11C1100

CPC分类号： G11C11/16 ,  B82Y10/00

摘要： Unwanted programming by stray magnetic fields is prevented in an MRAM configuration. Compensating currents that counteract the stray magnetic fields are strategically conducted through the MRAM configuration.

公开(公告)号：US07239537B2

公开(公告)日：2007-07-03

申请号：US10905585

申请日：2005-01-12

申请人： John K. DeBrosse ,  Dietmar Gogl ,  Stefan Lammers ,  Hans Viehmann

发明人： John K. DeBrosse ,  Dietmar Gogl ,  Stefan Lammers ,  Hans Viehmann

IPC分类号： G11C11/00

CPC分类号： G11C11/16 ,  G11C29/02 ,  G11C29/026 ,  G11C29/028 ,  G11C2029/1204

摘要： A calibrated magnetic random access memory (MRAM) current sense amplifier includes a first plurality of trim transistors selectively configured in parallel with a first load device, the first load device associated with a data side of the sense amplifier. A second plurality of trim transistors is selectively configured in parallel with a second load device, the second load device associated with a reference side of the sense amplifier. The first and said second plurality of trim transistors are individually activated so as to compensate for device mismatch with respect to the data and reference sides of the sense amplifier.

摘要翻译： 校准磁性随机存取存储器（MRAM）电流检测放大器包括与第一负载装置并联的第一多个调整晶体管，第一负载装置与读出放大器的数据侧相关联。 与第二负载装置并联地选择性地配置第二组微调晶体管，第二负载装置与感测放大器的参考侧相关联。 单独激活第一和第二多个微调晶体管，以补偿相对于读出放大器的数据和参考侧的器件失配。

公开(公告)号：US06545900B2

公开(公告)日：2003-04-08

申请号：US09951242

申请日：2001-09-12

申请人： Thomas Böhm ,  Dietmar Gogl ,  Martin Freitag ,  Stefan Lammers

发明人： Thomas Böhm ,  Dietmar Gogl ,  Martin Freitag ,  Stefan Lammers

IPC分类号： G11C1702

CPC分类号： G11C11/16 ,  G11C5/025 ,  H01L27/222

摘要： An MRAM module configuration in which, in order to increase the packing density, memory cell zones containing memory arrays and peripheral circuits are nested in one another. In this manner, an increased packing density of the memory cell is achieved which results in lowered production costs and a smaller chip space for a more compact configuration.

公开(公告)号：US06781896B2

公开(公告)日：2004-08-24

申请号：US10135416

申请日：2002-04-30

申请人： Stefan Lammers ,  Dietmar Gogl ,  Gerhard Müller

发明人： Stefan Lammers ,  Dietmar Gogl ,  Gerhard Müller

IPC分类号： G11C700

CPC分类号： G11C29/70

摘要： The MRAM semiconductor memory configuration has MRAM main cell arrays in the form of a crosspoint array or a transistor array together with redundant MRAM cell arrays formed of redundant MRAM memory cells arranged in a plurality of planes and provided on the same chip. The redundant MRAM cell arrays are distributed over the individual planes of the memory matrix or one plane of the memory array is used in its entirety for providing redundant cell arrays.

摘要翻译： MRAM半导体存储器配置具有交叉点阵列或晶体管阵列形式的MRAM主单元阵列以及布置在多个平面中并设置在同一芯片上的冗余MRAM存储单元形成的冗余MRAM单元阵列。 冗余MRAM单元阵列分布在存储器矩阵的各个平面上，或者整体使用存储器阵列的一个平面来提供冗余单元阵列。

公开(公告)号：US06744662B2

公开(公告)日：2004-06-01

申请号：US10436428

申请日：2003-05-12

申请人： Martin Freitag ,  Dietmar Gogl ,  Heinz Hoenigschmid ,  Stefan Lammers

发明人： Martin Freitag ,  Dietmar Gogl ,  Heinz Hoenigschmid ,  Stefan Lammers

IPC分类号： G11C1100

CPC分类号： H01L27/222 ,  B82Y10/00 ,  G11C11/16

摘要： The form of leads of a cell array of a multiplicity of magnetic memory cells is optimized by deviating from a square cross section of the leads in such a way that the magnetic field component of the write currents lying in the cell array plane decreases sufficiently rapidly with increasing distance from the crossover point. The cell array is constructed from a matrix of the column leads and the row leads.

摘要翻译： 多个磁存储器单元的单元阵列的引线的形式通过偏离引线的正方形横截面而被优化，使得位于单元阵列平面中的写入电流的磁场分量充分快速地减小， 增加距离交叉点的距离。 单元阵列由列引线和行引线的矩阵构成。

公开(公告)号：US20080310210A1

公开(公告)日：2008-12-18

申请号：US11818196

申请日：2007-06-13

申请人： Dietmar Gogl ,  Ulrich Klostermann

发明人： Dietmar Gogl ,  Ulrich Klostermann

IPC分类号： G11C7/02

CPC分类号： G11C13/0011 ,  G11C8/08 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2013/009 ,  G11C2213/79

摘要： A memory cell is disclosed. The memory cell comprises a storage element including a first terminal and a second terminal, and a select transistor including a first terminal, a second terminal and a control terminal. The voltage at the control terminal of the select transistor affects a current flowing between the first terminal and the second terminal. The first terminal of the select transistor is coupled to the second terminal of the storage element. A bit line is coupled to the first terminal of the storage element, a first word line is coupled to the control terminal of the select transistor, and a second word line is coupled to the second terminal of the select transistor.

摘要翻译： 公开了一种存储器单元。 存储单元包括存储元件，其包括第一端子和第二端子，以及选择晶体管，其包括第一端子，第二端子和控制端子。 选择晶体管的控制端子处的电压影响在第一端子和第二端子之间流动的电流。 选择晶体管的第一端子耦合到存储元件的第二端子。 位线耦合到存储元件的第一端子，第一字线耦合到选择晶体管的控制端子，第二字线耦合到选择晶体管的第二端子。

公开(公告)号：US07433253B2

公开(公告)日：2008-10-07

申请号：US11768508

申请日：2007-06-26

申请人： Dietmar Gogl ,  Hans-Heinrich Viehmann

发明人： Dietmar Gogl ,  Hans-Heinrich Viehmann

IPC分类号： G11C7/02 ,  G11C11/00

CPC分类号： G11C7/067 ,  G11C5/02 ,  G11C5/04 ,  G11C11/1673 ,  G11C11/5614 ,  G11C11/5664 ,  G11C11/5678 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0011 ,  G11C13/0014 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2207/063 ,  G11C2213/71 ,  G11C2213/79

摘要： An integrated circuit has a current sense amplifier that includes a voltage comparator having a first input, a second input and an output; a first clamping device coupled between the first input of the voltage comparator and a first input signal node, a second clamping device coupled between the second input of the voltage comparator and a second input signal node, a current mirror having a first side and a second side, the current mirror first side including a first transistor coupled between a voltage source and the first clamping device and the current mirror second side including a second transistor coupled between the voltage source and the second clamping device, and a sensing scheme including an actively balanced capacitance coupled to the source and drain of the second transistor.

摘要翻译： 集成电路具有电流检测放大器，其包括具有第一输入，第二输入和输出的电压比较器; 耦合在电压比较器的第一输入端和第一输入信号节点之间的第一钳位装置，耦合在电压比较器的第二输入端和第二输入信号节点之间的第二钳位装置，具有第一侧和第二 电流镜第一侧包括耦合在电压源和第一钳位装置之间的第一晶体管和电流镜第二侧，其包括耦合在电压源和第二钳位装置之间的第二晶体管，以及感测方案，包括主动平衡 耦合到第二晶体管的源极和漏极的电容。