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公开(公告)号：US08319274B2
公开(公告)日：2012-11-27
申请号：US11829248
申请日：2007-07-27
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , G11C16/0425 , G11C16/10 , H01L27/115 , H01L27/11568 , H01L29/66833
摘要： A gate dielectric functioning as a charge-trapping layer of a non-volatile memory cell with a structure of an insulator gate field effect transistor is formed by laminating a first insulator formed of a silicon oxide film, a second insulator formed of a silicon nitride film, a third insulator formed of a silicon nitride film containing oxygen, and a fourth insulator formed of a silicon oxide film in this order on a main surface of a semiconductor substrate. Holes are injected into the charge-trapping layer from a gate electrode side. Accordingly, since the operations can be achieved without the penetration of the holes through the interface in contact to the channel and the first insulator, the deterioration in rewriting endurance and the charge-trapping characteristics due to the deterioration of the first insulator does not occur, and highly efficient rewriting (writing and erasing) characteristics and stable charge-trapping characteristics can be achieved.
摘要翻译： 作为具有绝缘体栅极场效应晶体管的结构的非易失性存储单元的电荷捕获层的栅极介质通过层叠由氧化硅膜形成的第一绝缘体，由氮化硅膜形成的第二绝缘体 由半导体衬底的主表面依次由含有氧的氮化硅膜构成的第三绝缘体和由氧化硅膜形成的第四绝缘体构成。 孔从栅电极侧注入电荷捕获层。 因此，由于可以在没有孔穿过与沟道和第一绝缘体接触的界面的情况下实现操作，所以不会发生由于第一绝缘体的劣化导致的重写耐久性和电荷捕获特性的劣化， 并且可以实现高效的重写（写入和擦除）特性和稳定的电荷捕获特性。
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公开(公告)号：US08410543B2
公开(公告)日：2013-04-02
申请号：US11965391
申请日：2007-12-27
IPC分类号： H01L27/088
CPC分类号： H01L29/792 , G11C16/0466 , H01L21/28273 , H01L21/28282 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11568 , H01L27/11573 , H01L29/42344 , H01L29/513
摘要： In a non-volatile memory in which writing/erasing is performed by changing a total charge amount by injecting electrons and holes into a silicon nitride film serving as a charge accumulation layer, in order to realize a high efficiency of a hole injection from a gate electrode, the gate electrode of a memory cell comprises a laminated structure made of a plurality of polysilicon films with different impurity concentrations, for example, a two-layered structure comprising a p-type polysilicon film with a low impurity concentration and a p+-type polysilicon film with a high impurity concentration deposited thereon.
摘要翻译： 在通过将电子和空穴注入到用作电荷累积层的氮化硅膜中来改变总电荷量进行写/擦除的非易失性存储器中，为了实现从栅极的空穴注入的高效率 电极，存储单元的栅电极包括由具有不同杂质浓度的多个多晶硅膜制成的层压结构，例如包括具有低杂质浓度的p型多晶硅膜和p +型的双层结构 沉积有高杂质浓度的多晶硅膜。
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公开(公告)号：US20080185635A1
公开(公告)日：2008-08-07
申请号：US11965391
申请日：2007-12-27
IPC分类号： H01L27/088
CPC分类号： H01L29/792 , G11C16/0466 , H01L21/28273 , H01L21/28282 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11568 , H01L27/11573 , H01L29/42344 , H01L29/513
摘要： In a non-volatile memory in which writing/erasing is performed by changing a total charge amount by injecting electrons and holes into a silicon nitride film serving as a charge accumulation layer, in order to realize a high efficiency of a hole injection from a gate electrode, the gate electrode of a memory cell comprises a laminated structure made of a plurality of polysilicon films with different impurity concentrations, for example, a two-layered structure comprising a p-type polysilicon film with a low impurity concentration and a p+-type polysilicon film with a high impurity concentration deposited thereon.
摘要翻译： 在通过将电子和空穴注入到用作电荷累积层的氮化硅膜中来改变总电荷量进行写/擦除的非易失性存储器中，为了实现从栅极的空穴注入的高效率 电极，存储单元的栅电极包括由具有不同杂质浓度的多个多晶硅膜制成的层压结构，例如包括具有低杂质浓度的p型多晶硅膜的双层结构， 具有沉积在其上的高杂质浓度的+ 型多晶硅膜。
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4.发明授权公开(公告)号：US08409949B2
公开(公告)日：2013-04-02
申请号：US12822157
申请日：2010-06-23
IPC分类号： H01L21/336
CPC分类号： H01L29/42328 , G11C16/3418 , H01L27/11521 , H01L27/1203 , H01L29/7883
摘要： Provided is a nonvolatile semiconductor memory device highly integrated and highly reliable. A plurality of memory cells are formed in a plurality of active regions sectioned by a plurality of isolations (silicon oxide films) extending in the Y direction and deeper than a well (p type semiconductor region). In each memory cell, a contact is provided in the well (p type semiconductor region) so as to penetrate through a source diffusion layer (n+ type semiconductor region), and the contact that electrically connects bit lines (metal wirings) and the source diffusion layer (n+ type semiconductor region) is also electrically connected to the well (p type semiconductor region).
摘要翻译： 提供了高度集成且高度可靠的非易失性半导体存储器件。 多个存储单元形成在由在Y方向上延伸并且比阱（p型半导体区域）更深的多个隔离（氧化硅膜）分割的多个有源区域中。 在每个存储单元中，在阱（p型半导体区域）中提供接触以穿透源极扩散层（n +型半导体区域），并且将位线（金属布线）和源极扩散 层（n +型半导体区）也与阱（p型半导体区）电连接。
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5.发明申请公开(公告)号：US20090134449A1
公开(公告)日：2009-05-28
申请号：US12273308
申请日：2008-11-18
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/42328 , G11C16/3418 , H01L27/11521 , H01L27/1203 , H01L29/7883
摘要： Provided is a nonvolatile semiconductor memory device highly integrated and highly reliable. A plurality of memory cells are formed in a plurality of active regions sectioned by a plurality of isolations (silicon oxide films) extending in the Y direction and deeper than a well (p type semiconductor region). In each memory cell, a contact is provided in the well (p type semiconductor region) so as to penetrate through a source diffusion layer (n+ type semiconductor region), and the contact that electrically connects bit lines (metal wirings) and the source diffusion layer (n+ type semiconductor region) is also electrically connected to the well (p type semiconductor region).
摘要翻译： 提供了高度集成且高度可靠的非易失性半导体存储器件。 多个存储单元形成在由在Y方向上延伸并且比阱（p型半导体区域）更深的多个隔离（氧化硅膜）分割的多个有源区域中。 在每个存储单元中，在阱（p型半导体区域）中提供接触以穿透源极扩散层（n +型半导体区域），并且将位线（金属布线）和源极扩散 层（n +型半导体区）也与阱（p型半导体区）电连接。
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6.发明申请公开(公告)号：US20100261327A1
公开(公告)日：2010-10-14
申请号：US12822157
申请日：2010-06-23
IPC分类号： H01L21/336
CPC分类号： H01L29/42328 , G11C16/3418 , H01L27/11521 , H01L27/1203 , H01L29/7883
摘要： Provided is a nonvolatile semiconductor memory device highly integrated and highly reliable. A plurality of memory cells are formed in a plurality of active regions sectioned by a plurality of isolations (silicon oxide films) extending in the Y direction and deeper than a well (p type semiconductor region). In each memory cell, a contact is provided in the well (p type semiconductor region) so as to penetrate through a source diffusion layer (n+ type semiconductor region), and the contact that electrically connects bit lines (metal wirings) and the source diffusion layer (n+ type semiconductor region) is also electrically connected to the well (p type semiconductor region).
摘要翻译： 提供了高度集成且高度可靠的非易失性半导体存储器件。 多个存储单元形成在由在Y方向上延伸并且比阱（p型半导体区域）更深的多个隔离（氧化硅膜）分割的多个有源区域中。 在每个存储单元中，在阱（p型半导体区域）中提供接触以穿透源极扩散层（n +型半导体区域），并且将位线（金属布线）和源极扩散 层（n +型半导体区）也与阱（p型半导体区）电连接。
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7.发明授权公开(公告)号：US07759720B2
公开(公告)日：2010-07-20
申请号：US12273308
申请日：2008-11-18
IPC分类号： H01L29/94
CPC分类号： H01L29/42328 , G11C16/3418 , H01L27/11521 , H01L27/1203 , H01L29/7883
摘要： Provided is a nonvolatile semiconductor memory device highly integrated and highly reliable. A plurality of memory cells are formed in a plurality of active regions sectioned by a plurality of isolations (silicon oxide films) extending in the Y direction and deeper than a well (p type semiconductor region). In each memory cell, a contact is provided in the well (p type semiconductor region) so as to penetrate through a source diffusion layer (n+ type semiconductor region), and the contact that electrically connects bit lines (metal wirings) and the source diffusion layer (n+ type semiconductor region) is also electrically connected to the well (p type semiconductor region).
摘要翻译： 提供了高度集成且高度可靠的非易失性半导体存储器件。 多个存储单元形成在由在Y方向上延伸并且比阱（p型半导体区域）更深的多个隔离（氧化硅膜）分割的多个有源区域中。 在每个存储单元中，在阱（p型半导体区域）中提供接触以穿透源极扩散层（n +型半导体区域），并且将位线（金属布线）和源极扩散 层（n +型半导体区）也与阱（p型半导体区）电连接。
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公开(公告)号：US08385124B2
公开(公告)日：2013-02-26
申请号：US13075169
申请日：2011-03-29
IPC分类号： G11C16/04
CPC分类号： H01L21/28282 , G11C16/0466 , H01L27/11573 , H01L29/42344 , H01L29/66833 , H01L29/78 , H01L29/792
摘要： The semiconductor device includes the nonvolatile memory cell in the main surface of a semiconductor substrate. The nonvolatile memory cell has a first insulating film over the semiconductor substrate, a conductive film, a second insulating film, the charge storage film capable of storing therein charges, a third insulating film over the charge storage film, a first gate electrode, a fourth insulating film in contact with the set of stacked films from the first insulating film to the foregoing first gate electrode, a fifth insulating film juxtaposed with the first insulating film over the foregoing semiconductor substrate, a second gate electrode formed over the fifth insulating film to be adjacent to the foregoing first gate electrode over the side surface of the fourth insulating film, and source/drain regions with the first and second gate electrodes interposed therebetween. The conductive film and the charge storage film are formed to two-dimensionally overlap.
摘要翻译： 半导体器件包括在半导体衬底的主表面中的非易失性存储单元。 非易失性存储单元在半导体衬底上具有第一绝缘膜，导电膜，第二绝缘膜，能够存储电荷的电荷存储膜，电荷存储膜上的第三绝缘膜，第一栅电极，第四绝缘膜 绝缘膜与从第一绝缘膜到前述第一栅电极的层叠膜接触;第五绝缘膜，与上述半导体衬底上的第一绝缘膜并置，形成在第五绝缘膜上的第二栅电极， 与第四绝缘膜的侧表面上的上述第一栅电极相邻，以及其间插入第一和第二栅电极的源/漏区。 导电膜和电荷存储膜形成为二维重叠。
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公开(公告)号：US20110242888A1
公开(公告)日：2011-10-06
申请号：US13075169
申请日：2011-03-29
IPC分类号： G11C11/34 , H01L29/792 , H01L21/336
CPC分类号： H01L21/28282 , G11C16/0466 , H01L27/11573 , H01L29/42344 , H01L29/66833 , H01L29/78 , H01L29/792
摘要： The semiconductor device includes the nonvolatile memory cell in the main surface of a semiconductor substrate. The nonvolatile memory cell has a first insulating film over the semiconductor substrate, a conductive film, a second insulating film, the charge storage film capable of storing therein charges, a third insulating film over the charge storage film, a first gate electrode, a fourth insulating film in contact with the set of stacked films from the first insulating film to the foregoing first gate electrode, a fifth insulating film juxtaposed with the first insulating film over the foregoing semiconductor substrate, a second gate electrode formed over the fifth insulating film to be adjacent to the foregoing first gate electrode over the side surface of the fourth insulating film, and source/drain regions with the first and second gate electrodes interposed therebetween. The conductive film and the charge storage film are formed to two-dimensionally overlap.
摘要翻译： 半导体器件包括在半导体衬底的主表面中的非易失性存储单元。 非易失性存储单元在半导体衬底上具有第一绝缘膜，导电膜，第二绝缘膜，能够存储电荷的电荷存储膜，电荷存储膜上的第三绝缘膜，第一栅电极，第四绝缘膜 绝缘膜与从第一绝缘膜到前述第一栅电极的层叠膜接触;第五绝缘膜，与上述半导体衬底上的第一绝缘膜并置，形成在第五绝缘膜上的第二栅电极， 与第四绝缘膜的侧表面上的上述第一栅电极相邻，以及其间插入第一和第二栅电极的源/漏区。 导电膜和电荷存储膜形成为二维重叠。
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10.发明申请公开(公告)号：US20090309153A1
公开(公告)日：2009-12-17
申请号：US12481570
申请日：2009-06-09
申请人： Itaru YANAGI , Digh Hisamoto
发明人： Itaru YANAGI , Digh Hisamoto
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/792 , H01L27/11 , H01L27/11568 , H01L27/11573 , H01L29/66833
摘要： A process of forming a non-volatile memory in a memory region on a silicon substrate, in which a select gate electrode is formed on a main surface of the silicon substrate, and a dummy gate adjacent to one of sidewall surfaces of the electrode is formed. Then, memory source/drain regions are formed by ion implantation using the dummy gate as an ion implantation mask. Then, the dummy gate is removed, and a charge accumulating film and a memory gate electrode are sequentially formed at the part where the dummy gate has been provided, thereby forming a structure in which the memory source/drain regions are arranged at portions below and lateral to the memory gate electrode. In this process, the charge accumulating film and the memory gate electrode are formed after the ion implantation for forming the memory source/drain regions is carried out.
摘要翻译： 形成在硅衬底上的存储区域中的非易失性存储器的处理，其中在硅衬底的主表面上形成选择栅电极，并且与电极的一个侧壁表面相邻的虚拟栅极形成 。 然后，通过使用伪栅极作为离子注入掩模的离子注入形成存储源极/漏极区。 然后，去除伪栅极，并且在设置有虚设栅极的部分顺序地形成电荷累积膜和存储栅电极，从而形成其中存储器源极/漏极区域布置在下面的部分的结构，以及 侧向存储栅电极。 在该过程中，在用于形成存储器源极/漏极区域的离子注入之后形成电荷累积膜和存储栅电极。
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