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公开(公告)号：US08410543B2
公开(公告)日：2013-04-02
申请号：US11965391
申请日：2007-12-27
IPC分类号： H01L27/088
CPC分类号： H01L29/792 , G11C16/0466 , H01L21/28273 , H01L21/28282 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11568 , H01L27/11573 , H01L29/42344 , H01L29/513
摘要： In a non-volatile memory in which writing/erasing is performed by changing a total charge amount by injecting electrons and holes into a silicon nitride film serving as a charge accumulation layer, in order to realize a high efficiency of a hole injection from a gate electrode, the gate electrode of a memory cell comprises a laminated structure made of a plurality of polysilicon films with different impurity concentrations, for example, a two-layered structure comprising a p-type polysilicon film with a low impurity concentration and a p+-type polysilicon film with a high impurity concentration deposited thereon.
摘要翻译： 在通过将电子和空穴注入到用作电荷累积层的氮化硅膜中来改变总电荷量进行写/擦除的非易失性存储器中，为了实现从栅极的空穴注入的高效率 电极，存储单元的栅电极包括由具有不同杂质浓度的多个多晶硅膜制成的层压结构，例如包括具有低杂质浓度的p型多晶硅膜和p +型的双层结构 沉积有高杂质浓度的多晶硅膜。
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公开(公告)号：US20080185635A1
公开(公告)日：2008-08-07
申请号：US11965391
申请日：2007-12-27
IPC分类号： H01L27/088
CPC分类号： H01L29/792 , G11C16/0466 , H01L21/28273 , H01L21/28282 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11568 , H01L27/11573 , H01L29/42344 , H01L29/513
摘要： In a non-volatile memory in which writing/erasing is performed by changing a total charge amount by injecting electrons and holes into a silicon nitride film serving as a charge accumulation layer, in order to realize a high efficiency of a hole injection from a gate electrode, the gate electrode of a memory cell comprises a laminated structure made of a plurality of polysilicon films with different impurity concentrations, for example, a two-layered structure comprising a p-type polysilicon film with a low impurity concentration and a p+-type polysilicon film with a high impurity concentration deposited thereon.
摘要翻译： 在通过将电子和空穴注入到用作电荷累积层的氮化硅膜中来改变总电荷量进行写/擦除的非易失性存储器中，为了实现从栅极的空穴注入的高效率 电极，存储单元的栅电极包括由具有不同杂质浓度的多个多晶硅膜制成的层压结构，例如包括具有低杂质浓度的p型多晶硅膜的双层结构， 具有沉积在其上的高杂质浓度的+ 型多晶硅膜。
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公开(公告)号：US20080073705A1
公开(公告)日：2008-03-27
申请号：US11829248
申请日：2007-07-27
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , G11C16/0425 , G11C16/10 , H01L27/115 , H01L27/11568 , H01L29/66833
摘要： A gate dielectric functioning as a charge-trapping layer of a non-volatile memory cell with a structure of an insulator gate field effect transistor is formed by laminating a first insulator formed of a silicon oxide film, a second insulator formed of a silicon nitride film, a third insulator formed of a silicon nitride film containing oxygen, and a fourth insulator formed of a silicon oxide film in this order on a main surface of a semiconductor substrate. Holes are injected into the charge-trapping layer from a gate electrode side. Accordingly, since the operations can be achieved without the penetration of the holes through the interface in contact to the channel and the first insulator, the deterioration in rewriting endurance and the charge-trapping characteristics due to the deterioration of the first insulator does not occur, and highly efficient rewriting (writing and erasing) characteristics and stable charge-trapping characteristics can be achieved.
摘要翻译： 作为具有绝缘体栅极场效应晶体管的结构的非易失性存储单元的电荷捕获层的栅极介质通过层叠由氧化硅膜形成的第一绝缘体，由氮化硅膜形成的第二绝缘体 由半导体衬底的主表面依次由含有氧的氮化硅膜构成的第三绝缘体和由氧化硅膜形成的第四绝缘体构成。 孔从栅电极侧注入电荷捕获层。 因此，由于可以在没有孔穿过与沟道和第一绝缘体接触的界面的情况下实现操作，所以不会发生由于第一绝缘体的劣化导致的重写耐久性和电荷捕获特性的劣化， 并且可以实现高效的重写（写入和擦除）特性和稳定的电荷捕获特性。
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公开(公告)号：US08319274B2
公开(公告)日：2012-11-27
申请号：US11829248
申请日：2007-07-27
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , G11C16/0425 , G11C16/10 , H01L27/115 , H01L27/11568 , H01L29/66833
摘要： A gate dielectric functioning as a charge-trapping layer of a non-volatile memory cell with a structure of an insulator gate field effect transistor is formed by laminating a first insulator formed of a silicon oxide film, a second insulator formed of a silicon nitride film, a third insulator formed of a silicon nitride film containing oxygen, and a fourth insulator formed of a silicon oxide film in this order on a main surface of a semiconductor substrate. Holes are injected into the charge-trapping layer from a gate electrode side. Accordingly, since the operations can be achieved without the penetration of the holes through the interface in contact to the channel and the first insulator, the deterioration in rewriting endurance and the charge-trapping characteristics due to the deterioration of the first insulator does not occur, and highly efficient rewriting (writing and erasing) characteristics and stable charge-trapping characteristics can be achieved.
摘要翻译： 作为具有绝缘体栅极场效应晶体管的结构的非易失性存储单元的电荷捕获层的栅极介质通过层叠由氧化硅膜形成的第一绝缘体，由氮化硅膜形成的第二绝缘体 由半导体衬底的主表面依次由含有氧的氮化硅膜构成的第三绝缘体和由氧化硅膜形成的第四绝缘体构成。 孔从栅电极侧注入电荷捕获层。 因此，由于可以在没有孔穿过与沟道和第一绝缘体接触的界面的情况下实现操作，所以不会发生由于第一绝缘体的劣化导致的重写耐久性和电荷捕获特性的劣化， 并且可以实现高效的重写（写入和擦除）特性和稳定的电荷捕获特性。
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5.发明授权公开(公告)号：US08409949B2
公开(公告)日：2013-04-02
申请号：US12822157
申请日：2010-06-23
IPC分类号： H01L21/336
CPC分类号： H01L29/42328 , G11C16/3418 , H01L27/11521 , H01L27/1203 , H01L29/7883
摘要： Provided is a nonvolatile semiconductor memory device highly integrated and highly reliable. A plurality of memory cells are formed in a plurality of active regions sectioned by a plurality of isolations (silicon oxide films) extending in the Y direction and deeper than a well (p type semiconductor region). In each memory cell, a contact is provided in the well (p type semiconductor region) so as to penetrate through a source diffusion layer (n+ type semiconductor region), and the contact that electrically connects bit lines (metal wirings) and the source diffusion layer (n+ type semiconductor region) is also electrically connected to the well (p type semiconductor region).
摘要翻译： 提供了高度集成且高度可靠的非易失性半导体存储器件。 多个存储单元形成在由在Y方向上延伸并且比阱（p型半导体区域）更深的多个隔离（氧化硅膜）分割的多个有源区域中。 在每个存储单元中，在阱（p型半导体区域）中提供接触以穿透源极扩散层（n +型半导体区域），并且将位线（金属布线）和源极扩散 层（n +型半导体区）也与阱（p型半导体区）电连接。
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6.发明申请公开(公告)号：US20090134449A1
公开(公告)日：2009-05-28
申请号：US12273308
申请日：2008-11-18
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/42328 , G11C16/3418 , H01L27/11521 , H01L27/1203 , H01L29/7883
摘要： Provided is a nonvolatile semiconductor memory device highly integrated and highly reliable. A plurality of memory cells are formed in a plurality of active regions sectioned by a plurality of isolations (silicon oxide films) extending in the Y direction and deeper than a well (p type semiconductor region). In each memory cell, a contact is provided in the well (p type semiconductor region) so as to penetrate through a source diffusion layer (n+ type semiconductor region), and the contact that electrically connects bit lines (metal wirings) and the source diffusion layer (n+ type semiconductor region) is also electrically connected to the well (p type semiconductor region).
摘要翻译： 提供了高度集成且高度可靠的非易失性半导体存储器件。 多个存储单元形成在由在Y方向上延伸并且比阱（p型半导体区域）更深的多个隔离（氧化硅膜）分割的多个有源区域中。 在每个存储单元中，在阱（p型半导体区域）中提供接触以穿透源极扩散层（n +型半导体区域），并且将位线（金属布线）和源极扩散 层（n +型半导体区）也与阱（p型半导体区）电连接。
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7.发明申请公开(公告)号：US20100261327A1
公开(公告)日：2010-10-14
申请号：US12822157
申请日：2010-06-23
IPC分类号： H01L21/336
CPC分类号： H01L29/42328 , G11C16/3418 , H01L27/11521 , H01L27/1203 , H01L29/7883
摘要： Provided is a nonvolatile semiconductor memory device highly integrated and highly reliable. A plurality of memory cells are formed in a plurality of active regions sectioned by a plurality of isolations (silicon oxide films) extending in the Y direction and deeper than a well (p type semiconductor region). In each memory cell, a contact is provided in the well (p type semiconductor region) so as to penetrate through a source diffusion layer (n+ type semiconductor region), and the contact that electrically connects bit lines (metal wirings) and the source diffusion layer (n+ type semiconductor region) is also electrically connected to the well (p type semiconductor region).
摘要翻译： 提供了高度集成且高度可靠的非易失性半导体存储器件。 多个存储单元形成在由在Y方向上延伸并且比阱（p型半导体区域）更深的多个隔离（氧化硅膜）分割的多个有源区域中。 在每个存储单元中，在阱（p型半导体区域）中提供接触以穿透源极扩散层（n +型半导体区域），并且将位线（金属布线）和源极扩散 层（n +型半导体区）也与阱（p型半导体区）电连接。
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8.发明授权公开(公告)号：US07759720B2
公开(公告)日：2010-07-20
申请号：US12273308
申请日：2008-11-18
IPC分类号： H01L29/94
CPC分类号： H01L29/42328 , G11C16/3418 , H01L27/11521 , H01L27/1203 , H01L29/7883
摘要： Provided is a nonvolatile semiconductor memory device highly integrated and highly reliable. A plurality of memory cells are formed in a plurality of active regions sectioned by a plurality of isolations (silicon oxide films) extending in the Y direction and deeper than a well (p type semiconductor region). In each memory cell, a contact is provided in the well (p type semiconductor region) so as to penetrate through a source diffusion layer (n+ type semiconductor region), and the contact that electrically connects bit lines (metal wirings) and the source diffusion layer (n+ type semiconductor region) is also electrically connected to the well (p type semiconductor region).
摘要翻译： 提供了高度集成且高度可靠的非易失性半导体存储器件。 多个存储单元形成在由在Y方向上延伸并且比阱（p型半导体区域）更深的多个隔离（氧化硅膜）分割的多个有源区域中。 在每个存储单元中，在阱（p型半导体区域）中提供接触以穿透源极扩散层（n +型半导体区域），并且将位线（金属布线）和源极扩散 层（n +型半导体区）也与阱（p型半导体区）电连接。
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9.发明授权公开(公告)号：US07863134B2
公开(公告)日：2011-01-04
申请号：US12695271
申请日：2010-01-28
申请人： Hirotaka Hamamura , Itaru Yanagi , Toshiyuki Mine
发明人： Hirotaka Hamamura , Itaru Yanagi , Toshiyuki Mine
IPC分类号： H01L21/336
CPC分类号： H01L29/4234 , H01L21/28273 , H01L29/66825 , H01L29/792
摘要： A charge holding insulating film in a memory cell is constituted by a laminated film composed of a bottom insulating film, a charge storage film, and a top insulating film on a semiconductor substrate. Further, by performing a plasma nitriding treatment to the bottom insulating film, a nitride region whose nitrogen concentration has a peak value and is 1 atom % or more is formed on the upper surface side in the bottom insulating film. The thickness of the nitride region is set to 0.5 nm or more and 1.5 nm or less, and the peak value of nitrogen concentration is set to 5 atom % or more and 40 atom % or less, and a position of the peak value of nitrogen concentration is set within 2 nm from the upper surface of the bottom insulating film, thereby suppressing an interaction between the bottom insulating film and the charge storage film.
摘要翻译： 存储单元中的电荷保持绝缘膜由半导体衬底上的底部绝缘膜，电荷存储膜和顶部绝缘膜构成的层叠膜构成。 此外，通过对底部绝缘膜进行等离子体氮化处理，在底部绝缘膜的上表面侧形成氮浓度为1原子％以上的氮化物区域。 将氮化物区域的厚度设定为0.5nm以上至1.5nm以下，将氮浓度的峰值设定为5原子％以上且40原子％以下，将氮的峰值的位置 浓度从底部绝缘膜的上表面设定在2nm以内，从而抑制底部绝缘膜与电荷存储膜之间的相互作用。
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10.发明授权公开(公告)号：US07719051B2
公开(公告)日：2010-05-18
申请号：US12186488
申请日：2008-08-05
申请人： Hirotaka Hamamura , Itaru Yanagi , Toshiyuki Mine
发明人： Hirotaka Hamamura , Itaru Yanagi , Toshiyuki Mine
IPC分类号： H01L29/792
CPC分类号： H01L29/4234 , H01L21/28273 , H01L29/66825 , H01L29/792
摘要： A charge holding insulating film in a memory cell is constituted by a laminated film composed of a bottom insulating film, a charge storage film, and a top insulating film on a semiconductor substrate. Further, by performing a plasma nitriding treatment to the bottom insulating film, a nitride region whose nitrogen concentration has a peak value and is 1 atom % or more is formed on the upper surface side in the bottom insulating film. The thickness of the nitride region is set to 0.5 nm or more and 1.5 nm or less, and the peak value of nitrogen concentration is set to 5 atom % or more and 40 atom % or less, and a position of the peak value of nitrogen concentration is set within 2 nm from the upper surface of the bottom insulating film, thereby suppressing an interaction between the bottom insulating film and the charge storage film.
摘要翻译： 存储单元中的电荷保持绝缘膜由半导体衬底上的底部绝缘膜，电荷存储膜和顶部绝缘膜构成的层叠膜构成。 此外，通过对底部绝缘膜进行等离子体氮化处理，在底部绝缘膜的上表面侧形成氮浓度为1原子％以上的氮化物区域。 将氮化物区域的厚度设定为0.5nm以上至1.5nm以下，将氮浓度的峰值设定为5原子％以上且40原子％以下，将氮的峰值的位置 浓度从底部绝缘膜的上表面设定在2nm以内，从而抑制底部绝缘膜与电荷存储膜之间的相互作用。
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