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1.发明授权Multichip integration with through silicon via (TSV) die embedded in package 有权多芯片集成通过硅通孔（TSV）芯片嵌入封装公开(公告)号：US09000599B2
公开(公告)日：2015-04-07
申请号：US13893216
申请日：2013-05-13
IPC分类号： H01L23/00 , H01L23/522
CPC分类号： H01L25/50 , H01L21/4846 , H01L21/565 , H01L21/568 , H01L21/6835 , H01L23/3135 , H01L23/49816 , H01L23/49822 , H01L23/5226 , H01L23/5389 , H01L24/19 , H01L24/80 , H01L24/83 , H01L24/92 , H01L25/0657 , H01L2221/68372 , H01L2221/68381 , H01L2221/68386 , H01L2224/0401 , H01L2224/0508 , H01L2224/05111 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05164 , H01L2224/05169 , H01L2224/05541 , H01L2224/05568 , H01L2224/0557 , H01L2224/05644 , H01L2224/06181 , H01L2224/1134 , H01L2224/12105 , H01L2224/13005 , H01L2224/13023 , H01L2224/131 , H01L2224/16146 , H01L2224/2919 , H01L2224/32145 , H01L2224/73204 , H01L2224/73259 , H01L2224/8385 , H01L2224/9222 , H01L2225/06513 , H01L2225/06524 , H01L2225/06541 , H01L2225/06548 , H01L2225/06572 , H01L2924/01029 , H01L2924/12042 , H01L2924/181 , H01L2924/18162 , H01L2924/40501 , H01L2924/00014 , H01L2924/206 , H01L2924/00 , H01L2924/014
摘要： Embodiments of the present disclosure are directed to integrated circuit (IC) package assemblies with three-dimensional (3D) integration of multiple dies, as well as corresponding fabrication methods and systems incorporating such 3D IC package assemblies. A bumpless build-up layer (BBUL) package substrate may be formed on a first die, such as a microprocessor die. Laser radiation may be used to form an opening in a die backside film to expose TSV pads on the back side of the first die. A second die, such as a memory die stack, may be coupled to the first die by die interconnects formed between corresponding TSVs of the first and second dies. Underfill material may be applied to fill some or all of any remaining gap between the first and second dies, and/or an encapsulant may be applied over the second die and/or package substrate. Other embodiments may be described and/or claimed.
摘要翻译： 本公开的实施例涉及具有多个管芯的三维（3D）集成的集成电路（IC）封装组件，以及包含这种3D IC封装组件的相应制造方法和系统。 可以在诸如微处理器管芯的第一管芯上形成无凸起的堆积层（BBUL）封装衬底。 可以使用激光辐射在模具背面膜中形成开口，以暴露第一裸片背面的TSV焊盘。 诸如存储器管芯堆叠的第二管芯可以通过在第一和第二管芯的对应TSV之间形成的管芯互连而耦合到第一管芯。 可以施加底部填充材料以填充第一和第二管芯之间的任何剩余间隙中的一些或全部，和/或可以在第二管芯和/或封装衬底上施加密封剂。 可以描述和/或要求保护其他实施例。
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2.发明申请MULTICHIP INTEGRATION WITH THROUGH SILICON VIA (TSV) DIE EMBEDDED IN PACKAGE 有权通过嵌入式硅胶（TSV）封装的多芯片集成公开(公告)号：US20140332975A1
公开(公告)日：2014-11-13
申请号：US13893216
申请日：2013-05-13
IPC分类号： H01L23/522 , H01L23/00
CPC分类号： H01L25/50 , H01L21/4846 , H01L21/565 , H01L21/568 , H01L21/6835 , H01L23/3135 , H01L23/49816 , H01L23/49822 , H01L23/5226 , H01L23/5389 , H01L24/19 , H01L24/80 , H01L24/83 , H01L24/92 , H01L25/0657 , H01L2221/68372 , H01L2221/68381 , H01L2221/68386 , H01L2224/0401 , H01L2224/0508 , H01L2224/05111 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05164 , H01L2224/05169 , H01L2224/05541 , H01L2224/05568 , H01L2224/0557 , H01L2224/05644 , H01L2224/06181 , H01L2224/1134 , H01L2224/12105 , H01L2224/13005 , H01L2224/13023 , H01L2224/131 , H01L2224/16146 , H01L2224/2919 , H01L2224/32145 , H01L2224/73204 , H01L2224/73259 , H01L2224/8385 , H01L2224/9222 , H01L2225/06513 , H01L2225/06524 , H01L2225/06541 , H01L2225/06548 , H01L2225/06572 , H01L2924/01029 , H01L2924/12042 , H01L2924/181 , H01L2924/18162 , H01L2924/40501 , H01L2924/00014 , H01L2924/206 , H01L2924/00 , H01L2924/014
摘要： Embodiments of the present disclosure are directed to integrated circuit (IC) package assemblies with three-dimensional (3D) integration of multiple dies, as well as corresponding fabrication methods and systems incorporating such 3D IC package assemblies. A bumpless build-up layer (BBUL) package substrate may be formed on a first die, such as a microprocessor die. Laser radiation may be used to form an opening in a die backside film to expose TSV pads on the back side of the first die. A second die, such as a memory die stack, may be coupled to the first die by die interconnects formed between corresponding TSVs of the first and second dies. Underfill material may be applied to fill some or all of any remaining gap between the first and second dies, and/or an encapsulant may be applied over the second die and/or package substrate. Other embodiments may be described and/or claimed.
摘要翻译： 本公开的实施例涉及具有多个管芯的三维（3D）集成的集成电路（IC）封装组件，以及包含这种3D IC封装组件的对应的制造方法和系统。 可以在诸如微处理器管芯的第一管芯上形成无凸起的堆积层（BBUL）封装衬底。 可以使用激光辐射在模具背面膜中形成开口，以暴露第一裸片背面的TSV焊盘。 诸如存储器管芯堆叠的第二管芯可以通过在第一和第二管芯的对应TSV之间形成的管芯互连而耦合到第一管芯。 可以施加底部填充材料以填充第一和第二管芯之间的任何剩余间隙中的一些或全部，和/或可以在第二管芯和/或封装衬底上施加密封剂。 可以描述和/或要求保护其他实施例。
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公开(公告)号：US20120108450A1
公开(公告)日：2012-05-03
申请号：US12578428
申请日：2009-10-13
摘要： The invention provides for a receptor, capable of binding to a target molecule, linked to a hygroscopic polymer or hydrogel; and the use of this receptor in a device for detecting the target molecule in a gaseous and/or liquid phase. The invention also provides for a method for detecting the presence of a target molecule in the gas phase using the device. In particular, the receptor can be a peptide capable of binding a 2,4,6-trinitrotoluene (TNT) or 2,4-dinitrotoluene (DNT).
摘要翻译： 本发明提供能够结合到与吸湿性聚合物或水凝胶连接的靶分子的受体; 以及在用于在气相和/或液相中检测靶分子的装置中使用该受体。 本发明还提供了使用该装置在气相中检测靶分子的存在的方法。 特别地，受体可以是能够结合2,4,6-三硝基甲苯（TNT）或2,4-二硝基甲苯（DNT）的肽。
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4.发明授权公开(公告)号：US09041207B2
公开(公告)日：2015-05-26
申请号：US13931006
申请日：2013-06-28
IPC分类号： H01L23/528 , H01L23/00
CPC分类号： H01L23/528 , H01L21/486 , H01L21/568 , H01L21/6835 , H01L23/49816 , H01L23/49822 , H01L23/5389 , H01L24/19 , H01L24/82 , H01L2221/68372 , H01L2224/04105 , H01L2224/12105 , H01L2924/12042 , H01L2924/181 , H01L2924/18162 , H01L2924/00
摘要： An apparatus including a die including a dielectric material on a device side, an insulating layer surrounding a die area and embedding a thickness dimension of the die; and a carrier including a plurality of layers of conductive material disposed on the device side of the die, a first one of the layers of conductive materials being formed on the insulating layer and patterned into traces at least a portion of which are connected to respective contact points on the die. A method including disposing a die on a sacrificial substrate with a device side of the die opposite the sacrificial substrate; disposing a mold on the sacrificial substrate around; introducing an insulating material into a chase of the mold; removing the mold; forming a carrier on the insulating material adjacent a device side of a die; and separating the die and the carrier from the sacrificial substrate.
摘要翻译： 一种包括在器件侧具有介电材料的管芯的模具，围绕模具区域的绝缘层并嵌入所述管芯的厚度尺寸的装置; 以及载体，其包括设置在所述管芯的器件侧上的多个导电材料层，所述导电材料层中的第一层形成在所述绝缘层上并且被图案化为迹线，其至少一部分连接到相应的触点 点死亡 一种方法，包括在牺牲衬底上设置管芯，其中模具的器件侧与牺牲衬底相对; 在牺牲基板周围设置模具; 将绝缘材料引入模具的追逐中; 去除模具; 在邻近模具的装置侧的绝缘材料上形成载体; 以及将所述管芯和所述载体与所述牺牲衬底分离。
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公开(公告)号：US08957013B2
公开(公告)日：2015-02-17
申请号：US12578428
申请日：2009-10-13
IPC分类号： G01N25/50 , G01N33/22 , C40B40/10 , C07K7/06 , C07K7/08 , C40B30/04 , C40B60/12 , G01N33/566 , A61K38/00
摘要： The invention provides for a receptor, capable of binding to a target molecule, linked to a hygroscopic polymer or hydrogel; and the use of this receptor in a device for detecting the target molecule in a gaseous and/or liquid phase. The invention also provides for a method for detecting the presence of a target molecule in the gas phase using the device. In particular, the receptor can be a peptide capable of binding a 2,4,6-trinitrotoluene (TNT) or 2,4,-dinitrotoluene (DNT).
摘要翻译： 本发明提供能够结合到与吸湿性聚合物或水凝胶连接的靶分子的受体; 以及在用于在气相和/或液相中检测靶分子的装置中使用该受体。 本发明还提供了使用该装置在气相中检测靶分子的存在的方法。 特别地，该受体可以是能够结合2,4,6-三硝基甲苯（TNT）或2,4'-二硝基甲苯（DNT）的肽。
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6.发明申请BUMPLESS BUILD-UP LAYER (BBUL) SEMICONDUCTOR PACKAGE WITH ULTRA-THIN DIELECTRIC LAYER 有权无刷建立层（BBUL）半导体封装超薄电介质层公开(公告)号：US20140264830A1
公开(公告)日：2014-09-18
申请号：US13801859
申请日：2013-03-13
IPC分类号： H01L23/498
CPC分类号： H01L23/49822 , H01L21/76807 , H01L21/7681 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L24/19 , H01L2221/1026 , H01L2224/12105 , H01L2924/18162
摘要： Bumpless build-up layer (BBUL) semiconductor packages with ultra-thin dielectric layers are described. For example, an apparatus includes a semiconductor die including an integrated circuit having a plurality of external conductive bumps. A semiconductor package houses the semiconductor die. The semiconductor package includes a dielectric layer disposed above the plurality of external conductive bumps. A conductive via is disposed in the dielectric layer and coupled to one of the plurality of conductive bumps. A conductive line is disposed on the dielectric layer and coupled to the conductive via.
摘要翻译： 描述了具有超薄电介质层的无创积层（BBUL）半导体封装。 例如，一种装置包括具有多个外部导电凸块的集成电路的半导体管芯。 半导体封装容纳半导体管芯。 半导体封装包括设置在多个外部导电凸块上方的电介质层。 导电通孔设置在电介质层中并耦合到多个导电凸块之一。 导电线设置在电介质层上并耦合到导电通孔。
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7.发明授权Bumpless build-up layer (BBUL) semiconductor package with ultra-thin dielectric layer 有权无创积层（BBUL）半导体封装，具有超薄介电层公开(公告)号：US09520350B2
公开(公告)日：2016-12-13
申请号：US13801859
申请日：2013-03-13
IPC分类号： H01L23/498 , H01L23/532 , H01L21/768 , H01L23/00
CPC分类号： H01L23/49822 , H01L21/76807 , H01L21/7681 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L24/19 , H01L2221/1026 , H01L2224/12105 , H01L2924/18162
摘要： Bumpless build-up layer (BBUL) semiconductor packages with ultra-thin dielectric layers are described. For example, an apparatus includes a semiconductor die including an integrated circuit having a plurality of external conductive bumps. A semiconductor package houses the semiconductor die. The semiconductor package includes a dielectric layer disposed above the plurality of external conductive bumps. A conductive via is disposed in the dielectric layer and coupled to one of the plurality of conductive bumps. A conductive line is disposed on the dielectric layer and coupled to the conductive via.
摘要翻译： 描述了具有超薄电介质层的无创积层（BBUL）半导体封装。 例如，一种装置包括具有多个外部导电凸块的集成电路的半导体管芯。 半导体封装容纳半导体管芯。 半导体封装包括设置在多个外部导电凸块上方的电介质层。 导电通孔设置在电介质层中并耦合到多个导电凸块之一。 导电线设置在电介质层上并耦合到导电通孔。
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