公开(公告)号：US09041207B2

公开(公告)日：2015-05-26

申请号：US13931006

申请日：2013-06-28

申请人： Digvijay A. Raorane ,  Sairam Agraharam

发明人： Digvijay A. Raorane ,  Sairam Agraharam

IPC分类号： H01L23/528 ,  H01L23/00

CPC分类号： H01L23/528 ,  H01L21/486 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/82 ,  H01L2221/68372 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/00

摘要： An apparatus including a die including a dielectric material on a device side, an insulating layer surrounding a die area and embedding a thickness dimension of the die; and a carrier including a plurality of layers of conductive material disposed on the device side of the die, a first one of the layers of conductive materials being formed on the insulating layer and patterned into traces at least a portion of which are connected to respective contact points on the die. A method including disposing a die on a sacrificial substrate with a device side of the die opposite the sacrificial substrate; disposing a mold on the sacrificial substrate around; introducing an insulating material into a chase of the mold; removing the mold; forming a carrier on the insulating material adjacent a device side of a die; and separating the die and the carrier from the sacrificial substrate.

摘要翻译： 一种包括在器件侧具有介电材料的管芯的模具，围绕模具区域的绝缘层并嵌入所述管芯的厚度尺寸的装置; 以及载体，其包括设置在所述管芯的器件侧上的多个导电材料层，所述导电材料层中的第一层形成在所述绝缘层上并且被图案化为迹线，其至少一部分连接到相应的触点 点死亡 一种方法，包括在牺牲衬底上设置管芯，其中模具的器件侧与牺牲衬底相对; 在牺牲基板周围设置模具; 将绝缘材料引入模具的追逐中; 去除模具; 在邻近模具的装置侧的绝缘材料上形成载体; 以及将所述管芯和所述载体与所述牺牲衬底分离。

公开(公告)号：US08970051B2

公开(公告)日：2015-03-03

申请号：US13930889

申请日：2013-06-28

申请人： Hualiang Shi ,  Shengquan E. Ou ,  Sairam Agraharam ,  Tyler N. Osborn

发明人： Hualiang Shi ,  Shengquan E. Ou ,  Sairam Agraharam ,  Tyler N. Osborn

IPC分类号： H01L23/52 ,  H01L23/48 ,  H01L23/02 ,  H01L23/488 ,  H01L21/44 ,  H01L21/50 ,  H01L21/768 ,  H01L23/498

CPC分类号： H01L24/14 ,  H01L23/3114 ,  H01L23/49811 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L25/0657 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/05555 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/113 ,  H01L2224/11428 ,  H01L2224/11849 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/1403 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06565 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/014

摘要： A method including forming a contact pad array on an integrated circuit substrate, the contact pad array including a first plurality of contact pads and a second plurality of contact pads, wherein an accessible area of each of the first plurality of contact pads is different than an accessible area of each of the second plurality of contact pads; and depositing solder on the accessible area of the contact pads. An apparatus including an integrated circuit substrate including a body having a nonplanar shape and a surface including a first plurality of contact pads and a second plurality of contact pads, wherein an accessible area of each of the first plurality of contact pads is different than an accessible area of each of the second plurality of contact pads.

摘要翻译： 一种包括在集成电路基板上形成接触焊盘阵列的方法，所述接触焊盘阵列包括第一多个接触焊盘和第二多个接触焊盘，其中所述第一多个接触焊盘中的每一个的可访问区域不同于 第二多个接触垫中的每一个的可访问区域; 以及将焊料沉积在接触垫的可接近区域上。 一种装置，包括集成电路基板，其包括具有非平面形状的主体和包括第一多个接触焊盘和第二多个接触焊盘的表面，其中，所述第一多个接触焊盘中的每一个的可访问区域不同于可访问的 每个第二多个接触垫的面积。

公开(公告)号：US07659192B2

公开(公告)日：2010-02-09

申请号：US11648498

申请日：2006-12-29

申请人： Andrew Yeohi ,  Guotao Wang ,  Sairam Agraharam ,  Sudarshan Rangaraj

发明人： Andrew Yeohi ,  Guotao Wang ,  Sairam Agraharam ,  Sudarshan Rangaraj

IPC分类号： H01L21/44

CPC分类号： H01L24/13 ,  H01L24/11 ,  H01L24/81 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： Methods of forming a microelectronic device and associated structures are described. Those methods may comprise forming a die-side conductive interconnect on a substrate, wherein the die-side conductive interconnect comprises a columnar portion and a base portion, and wherein a diameter of the base portion is greater than a diameter of the columnar portion.

摘要翻译： 描述形成微电子器件和相关结构的方法。 这些方法可以包括在衬底上形成裸片侧导电互连，其中裸片侧导电互连包括柱状部分和基部，并且其中基部的直径大于柱状部分的直径。

公开(公告)号：US20080157392A1

公开(公告)日：2008-07-03

申请号：US12044202

申请日：2008-03-07

申请人： Andrew Yeohi ,  Guotao Wang ,  Sairam Agraharam ,  Sudarshan Rangaraj

发明人： Andrew Yeohi ,  Guotao Wang ,  Sairam Agraharam ,  Sudarshan Rangaraj

IPC分类号： H01L23/498

CPC分类号： H01L24/13 ,  H01L24/11 ,  H01L24/81 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： Methods of forming a microelectronic device and associated structures are described. Those methods may comprise forming a die-side conductive interconnect on a substrate, wherein the die-side conductive interconnect comprises a columnar portion and a base portion, and wherein a diameter of the base portion is greater than a diameter of the columnar portion.

摘要翻译： 描述形成微电子器件和相关结构的方法。 这些方法可以包括在衬底上形成裸片侧导电互连，其中裸片侧导电互连包括柱状部分和基部，并且其中基部的直径大于柱状部分的直径。

公开(公告)号：US06921706B2

公开(公告)日：2005-07-26

申请号：US10773879

申请日：2004-02-06

申请人： Gregory M. Chrysler ,  Abhay A. Watwe ,  Sairam Agraharam ,  Kramadhati V. Ravi ,  Michael C. Garner

发明人： Gregory M. Chrysler ,  Abhay A. Watwe ,  Sairam Agraharam ,  Kramadhati V. Ravi ,  Michael C. Garner

IPC分类号： H01L23/34 ,  H01L21/20 ,  H01L21/762 ,  H01L23/373 ,  H01L21/46 ,  H01L21/301 ,  H01L21/78

CPC分类号： H01L21/6835 ,  H01L21/2007 ,  H01L21/76254 ,  H01L23/3732 ,  H01L24/27 ,  H01L24/81 ,  H01L2221/68354 ,  H01L2221/68359 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/274 ,  H01L2224/73253 ,  H01L2224/81001 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/00 ,  H01L2224/05599

摘要： Processes are described whereby a wafer is manufactured, a die from the wafer, and an electronic assembly including the die. The die has a diamond layer which primarily serves to spread heat from hot spots of an integrated circuit in the die.

摘要翻译： 描述制造晶片的工艺，来自晶片的模具和包括模具的电子组件。 模具具有金刚石层，其主要用于从模具中的集成电路的热点散发热量。

公开(公告)号：US09526285B2

公开(公告)日：2016-12-27

申请号：US13717909

申请日：2012-12-18

申请人： Aleksandar Aleksov ,  Ravindranath V. Mahajan ,  Sairam Agraharam ,  Ian A. Young ,  John C. Johnson ,  Debendra Mallik ,  John S. Guzek

发明人： Aleksandar Aleksov ,  Ravindranath V. Mahajan ,  Sairam Agraharam ,  Ian A. Young ,  John C. Johnson ,  Debendra Mallik ,  John S. Guzek

IPC分类号： H05K1/02 ,  H05K3/30 ,  A41D31/00 ,  H05K1/03 ,  H05K1/18 ,  H05K3/32 ,  H05K3/34

CPC分类号： A41D31/00 ,  H05K1/0274 ,  H05K1/038 ,  H05K1/188 ,  H05K3/323 ,  H05K3/3436 ,  Y10T29/4913

摘要： A flexible computing fabric and a method of forming thereof. The flexible computing fabric includes an electronic substrate including one or more channels and including at least two ends. At least one computational element is mounted on the electronic substrate between the two ends and at least one functional element is mounted on the electronic substrate between the two ends. The channels form an interconnect between the elements. In addition, the electronic substrate is flexible and exhibits a flexural modulus in the range of 0.1 GPa to 30 GPa.

摘要翻译： 一种灵活的计算结构及其形成方法。 柔性计算结构包括包括一个或多个通道并且包括至少两个端部的电子基板。 至少一个计算元件安装在两端之间的电子基板上，并且至少一个功能元件安装在两端之间的电子基板上。 通道形成元件之间的互连。 此外，电子基板是柔性的并且具有在0.1GPa至30GPa范围内的挠曲模量。

公开(公告)号：US08952532B2

公开(公告)日：2015-02-10

申请号：US13893193

申请日：2013-05-13

申请人： Tieyu Zheng ,  Sumit Kumar ,  Sridhar Nara ,  Renee D. Garcia ,  Manohar S. Konchady ,  Suresh B. Yeruva ,  Lynn H. Chen ,  Tyler N. Osborn ,  Sairam Agraharam

发明人： Tieyu Zheng ,  Sumit Kumar ,  Sridhar Nara ,  Renee D. Garcia ,  Manohar S. Konchady ,  Suresh B. Yeruva ,  Lynn H. Chen ,  Tyler N. Osborn ,  Sairam Agraharam

IPC分类号： H01L23/48 ,  H01L23/498 ,  H01L21/768

CPC分类号： H01L24/81 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49894 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/17 ,  H01L2224/0603 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/1413 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/81193 ,  H01L2224/812 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/2064 ,  H01L2924/20643 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/014

摘要： An integrated circuit (IC) package stack with a first and second substrate interconnected by solder further includes solder resist openings (SRO) of mixed lateral dimension are spatially varied across an area of the substrates. In embodiments, SRO dimension is varied between at least two different diameters as a function of an estimated gap between the substrates that is dependent on location within the substrate area. In embodiments where deflection in at least one substrate reduces conformality between the substrates, a varying solder joint height is provided from a fixed volume of solder by reducing the lateral dimensioning of the SRO in regions of larger gap relative to SRO dimensions in regions of smaller gap. In embodiments, the first substrate may be any of an IC chip, package substrate, or interposer while the second substrate may be any of another IC chip, package substrate, interposer, or printed circuit board (PCB).

摘要翻译： 具有通过焊料互连的第一和第二衬底的集成电路（IC）封装堆栈还包括混合侧向尺寸的阻焊剂开口（SRO）在衬底的一个区域上空间变化。 在实施例中，SRO尺寸在至少两个不同直径之间变化，作为取决于衬底区域内的位置的衬底之间的估计间隙的函数。 在至少一个衬底中的偏转减小衬底之间的共形性的实施例中，通过在较小间隙的区域中相对于SRO尺寸的较大间隙的区域中减小SRO的横向尺寸，从固定体积的焊料提供变化的焊点高度 。 在实施例中，第一基板可以是IC芯片，封装基板或插入件中的任何一个，而第二基板可以是另一个IC芯片，封装基板，插入件或印刷电路板（PCB）中的任何一个。

公开(公告)号：US07517787B2

公开(公告)日：2009-04-14

申请号：US11087180

申请日：2005-03-22

申请人： Sairam Agraharam ,  Carlton Hanna ,  Dongming He ,  Vasudeva Atluri ,  Debendra Mallik ,  Matthew Escobido ,  Sujit Sharan

发明人： Sairam Agraharam ,  Carlton Hanna ,  Dongming He ,  Vasudeva Atluri ,  Debendra Mallik ,  Matthew Escobido ,  Sujit Sharan

IPC分类号： H01L23/48

CPC分类号： H01L24/13 ,  H01L24/11 ,  H01L24/16 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05568 ,  H01L2224/05655 ,  H01L2224/13 ,  H01L2224/13017 ,  H01L2224/13099 ,  H01L2224/16058 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/05099

摘要： In one embodiment, the invention provides a method comprising fabricating a die bump on a die, the die bump being shaped and dimensioned to at least reduce the flow of solder material used, to attach the die bump to a package substrate, towards an under bump metallurgy (UBM) layer located below the die bump. Advantageously, the method may comprise performing a substrate reflow operation to attach the package substrate to the die bump, without performing a separate wafer reflow operation to reflow the die bump.

摘要翻译： 在一个实施例中，本发明提供了一种方法，其包括在管芯上制造管芯凸块，所述管芯凸块的形状和尺寸被设计成至少减小所使用的焊料材料的流动，以将管芯凸块附接到封装衬底 位于模具凸块下方的冶金（UBM）层。 有利地，该方法可以包括执行衬底回流操作以将封装衬底附接到管芯凸块，而不执行单独的晶片回流操作以回流管芯凸块。

公开(公告)号：US07432532B2

公开(公告)日：2008-10-07

申请号：US11496934

申请日：2006-07-31

申请人： Gregory M. Chrysler ,  Abhay A. Watwe ,  Sairam Agraharam ,  Kramadhati V Ravi ,  Michael C. Garner

发明人： Gregory M. Chrysler ,  Abhay A. Watwe ,  Sairam Agraharam ,  Kramadhati V Ravi ,  Michael C. Garner

IPC分类号： H01L21/00

CPC分类号： H01L21/6835 ,  H01L21/2007 ,  H01L21/76254 ,  H01L23/3732 ,  H01L24/27 ,  H01L24/81 ,  H01L2221/68354 ,  H01L2221/68359 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/274 ,  H01L2224/73253 ,  H01L2224/81001 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/00 ,  H01L2224/05599

摘要： Processes are described whereby a wafer is manufactured, a die from the wafer, and an electronic assembly including the die. The die has a diamond layer which primarily serves to spread heat from hot spots of an integrated circuit in the die.

摘要翻译： 描述制造晶片的工艺，来自晶片的模具和包括模具的电子组件。 模具具有金刚石层，其主要用于从模具中的集成电路的热点散发热量。

公开(公告)号：US20220270976A1

公开(公告)日：2022-08-25

申请号：US17183132

申请日：2021-02-23

申请人： Xiaoxuan Sun ,  Purushotham Kaushik Muthur Srinath ,  Sairam Agraharam

发明人： Xiaoxuan Sun ,  Purushotham Kaushik Muthur Srinath ,  Sairam Agraharam

IPC分类号： H01L23/538 ,  H01L25/065 ,  H01L23/00

摘要： Disclosed herein are microelectronic assemblies including bridges, as well as related methods. In some embodiments, a microelectronic assembly may include a bridge in a mold material.