公开(公告)号：US07642656B2

公开(公告)日：2010-01-05

申请号：US12068867

申请日：2008-02-12

申请人： Do-Jae Yoo ,  Young-Do Kweon ,  Seog-Moon Choi ,  Burn-Sik Jang ,  Tae-Sung Jeong

发明人： Do-Jae Yoo ,  Young-Do Kweon ,  Seog-Moon Choi ,  Burn-Sik Jang ,  Tae-Sung Jeong

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L25/105 ,  H01L23/3128 ,  H01L24/73 ,  H01L25/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/0401

摘要： A semiconductor package, which includes: a first substrate, on which a pre-designed pattern is formed; a first chip, mounted by a flip chip method on one side of the first substrate; a first molding, covering the first substrate and the first chip; a first via, which penetrates the first molding, and which is electrically connected with the pattern formed on the first substrate; an interposer, which is placed on the first molding, and on both sides of which a pre-designed pattern is formed respectively; a second via, penetrating the interposer and electrically connecting both sides of the interposer; a second substrate, placed on the interposer with at least one conductive ball positioned in-between, such that the second substrate is electrically connected with the pattern formed on the interposer; and a second chip mounted on the second substrate, can be used to improve heat release and increase the degree of integration.

摘要翻译： 一种半导体封装件，包括：第一衬底，其上形成预先设计的图案; 第一芯片，通过倒装芯片方法安装在第一基板的一侧上; 第一模制件，覆盖第一基板和第一芯片; 第一通孔，其穿过第一模制件，并且与形成在第一基板上的图案电连接; 插入器，其被放置在第一模制件上，并且其两侧分别形成预先设计的图案; 第二通孔，穿透插入器并电连接插入器的两侧; 第二基板，放置在插入件上，其中至少一个导电球定位在其间，使得第二基板与形成在插入件上的图案电连接; 并且安装在第二基板上的第二芯片可用于改善散热并增加集成度。

公开(公告)号：US20080308950A1

公开(公告)日：2008-12-18

申请号：US12068867

申请日：2008-02-12

申请人： Do Jae Yoo ,  Young Do Kweon ,  Seog-Moon Choi ,  Burn-Sik Jang ,  Tae-Sung Jeong

发明人： Do Jae Yoo ,  Young Do Kweon ,  Seog-Moon Choi ,  Burn-Sik Jang ,  Tae-Sung Jeong

IPC分类号： H01L23/52 ,  H01L21/00

CPC分类号： H01L25/105 ,  H01L23/3128 ,  H01L24/73 ,  H01L25/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/0401

摘要： A semiconductor package, which includes: a first substrate, on which a pre-designed pattern is formed; a first chip, mounted by a flip chip method on one side of the first substrate; a first molding, covering the first substrate and the first chip; a first via, which penetrates the first molding, and which is electrically connected with the pattern formed on the first substrate; an interposer, which is placed on the first molding, and on both sides of which a pre-designed pattern is formed respectively; a second via, penetrating the interposer and electrically connecting both sides of the interposer; a second substrate, placed on the interposer with at least one conductive ball positioned in-between, such that the second substrate is electrically connected with the pattern formed on the interposer; and a second chip mounted on the second substrate, can be used to improve heat release and increase the degree of integration.

摘要翻译： 一种半导体封装件，包括：第一衬底，其上形成预先设计的图案; 第一芯片，通过倒装芯片方法安装在第一基板的一侧上; 第一模制件，覆盖第一基板和第一芯片; 第一通孔，其穿过第一模制件，并且与形成在第一基板上的图案电连接; 插入器，其被放置在第一模制件上，并且其两侧分别形成预先设计的图案; 第二通孔，穿透插入器并电连接插入器的两侧; 第二衬底，放置在插入器上，其中至少一个导电球位于其间，使得第二衬底与形成在插入件上的图案电连接; 并且安装在第二基板上的第二芯片可用于改善散热并增加集成度。