公开(公告)号：US11068018B2

公开(公告)日：2021-07-20

申请号：US16377761

申请日：2019-04-08

Applicant: Dolphin Design

Inventor： Mathieu Louvat ,  Lionel Jure ,  Gauthier Reveret ,  Alexandre Charvier

IPC: G06F1/08 ,  G06F1/10 ,  G06F1/3287 ,  G06F1/3296 ,  G06F1/324 ,  G06F9/445 ,  G06F1/3206 ,  G06F1/04 ,  G06F1/06

Abstract: The invention concerns a computing system comprising: an island (102) comprising a group of circuits capable of operating in one of a plurality of operating modes, the island being coupled to an island control circuit (122); and a clock generation circuit (902) supplying a further clock signal to the island control circuit (122) for controlling a change of mode of the island, the clock generation circuit (902) being configured to select one of a plurality of clock frequencies for the further clock signal, the selection being based on the change of operating mode to be applied.

公开(公告)号：US20190235567A1

公开(公告)日：2019-08-01

申请号：US16377761

申请日：2019-04-08

Applicant: Dolphin Design

Inventor： Mathieu Louvat ,  Lionel Jure ,  Gauthier Reveret ,  Alexandre Charvier

IPC: G06F1/08 ,  G06F1/10 ,  G06F1/324 ,  G06F1/3296 ,  G06F1/3287

CPC classification number: G06F1/08 ,  G06F1/10 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296

Abstract: The invention concerns a computing system comprising: an island (102) comprising a group of circuits capable of operating in one of a plurality of operating modes, the island being coupled to an island control circuit (122); and a clock generation circuit (902) supplying a further clock signal to the island control circuit (122) for controlling a change of mode of the island, the clock generation circuit (902) being configured to select one of a plurality of clock frequencies for the further clock signal, the selection being based on the change of operating mode to be applied.

公开(公告)号：US12169221B2

公开(公告)日：2024-12-17

申请号：US17468982

申请日：2021-09-08

Applicant: Dolphin Design

Inventor： Sebastien Genevey ,  Mathieu Louvat ,  Lionel Jure

IPC: G06F1/08 ,  G01R31/30 ,  G01R31/317 ,  G06F1/3203 ,  H03K3/011 ,  H03K5/134 ,  H03K5/00

Abstract: The present disclosure relates to an adaptive body biasing or voltage regulation circuit for a circuit region, comprising: a first delay module configured to delay a local clock signal to generate first and second output signals delayed by first and second delays; a multiplexer configured to select one of the first and second output signals; a first slack monitor circuit configured to generate a first detection signal indicating when a slack time of the first and second output signals is less than a first threshold; a voltage generation circuit configured to generate a supply voltage for the circuit region, or at least one biasing voltage for biasing wells of transistors in the circuit region, using a further control loop comprising a process, voltage and/or temperature sensor; and a control circuit configured to adjust a gain of the further control loop based on the first detection signal.

公开(公告)号：US11068630B2

公开(公告)日：2021-07-20

申请号：US16723069

申请日：2019-12-20

Applicant: Dolphin Design

Inventor： Mathieu Louvat ,  Lionel Jure ,  Vincent Huard

IPC: G06F30/327 ,  G06F30/3312 ,  H03K19/00 ,  H03K19/017 ,  H03K19/096 ,  G06F119/12 ,  G06F117/04

Abstract: Embodiments of the present technology provide a synchronous device. The synchronous device provides a first latch configured to store a data input signal during a first state of a first clock signal and a slack guard circuit. The slack guard circuit provides a delay element coupled to the first latch and configured to generate a delayed data signal, a gated-input cell coupled to the delay element and configured to propagate the delayed data signal during the first state of the first clock signal, and a comparator coupled to the first latch and the gated-input cell.