公开(公告)号：US20050083763A1

公开(公告)日：2005-04-21

申请号：US10961576

申请日：2004-10-08

申请人： Donald Morgan ,  Todd Merritt

发明人： Donald Morgan ,  Todd Merritt

IPC分类号： G11C5/06 ,  G11C8/00 ,  G11C8/12 ,  G11C11/408

CPC分类号： G11C11/408 ,  G11C5/06 ,  G11C8/00

摘要： A memory integrated circuit can be used either alone or as a pair to provide a memory device having twice the capacity of the single integrated circuit. The larger capacity memory device is addressed using an extra row address bit. The extra row address bit is used either to alternately enable each of the memory integrated circuits in one configuration or is remapped to become an extra column address bit in another configuration.

公开(公告)号：US20050276104A1

公开(公告)日：2005-12-15

申请号：US11207919

申请日：2005-08-19

申请人： Todd Merritt ,  Donald Morgan

发明人： Todd Merritt ,  Donald Morgan

IPC分类号： G11C7/10 ,  G11C11/34 ,  G11C11/4096

CPC分类号： G11C7/106 ,  G11C7/1036 ,  G11C7/1051 ,  G11C7/1069 ,  G11C11/4096 ,  G11C2207/107

摘要： A memory device for reducing the number of data read lines needed in a memory device. Specifically, multiple helper flip-flops are used to prefetch data in a memory device. The helper flip-flops are configured to latch one or two of the data bits from a 4-bit prefetch in an alternating periodic fashion, thereby necessitating fewer data lines.

摘要翻译： 一种用于减少存储器件中所需的数据读取线数量的存储器件。 具体来说，使用多个辅助触发器来预取存储器件中的数据。 辅助触发器被配置为以交替周期性方式从4位预取中锁存一个或两个数据位，从而需要更少的数据线。

公开(公告)号：US08143966B2

公开(公告)日：2012-03-27

申请号：US12902914

申请日：2010-10-12

申请人： Todd Merritt

发明人： Todd Merritt

IPC分类号： H01P3/02

CPC分类号： H01P3/026 ,  H01P3/081

摘要： Methods and apparatus are disclosed, such as those involving an interconnection layout for an integrated circuit (IC). One such layout includes a plurality of differential pairs of lines. Each differential pair has two lines including one or more parallel portions extending substantially parallel to each other. Each pair also includes a shield line. Each of the shield lines includes one or more parallel portions interposed between the parallel portions of one of the pairs of differential lines. One or more of the shield lines are electrically connected to a voltage reference, such as ground. This layout is believed to reduce or eliminate intra-pair coupling as well as inter-pair coupling.

摘要翻译： 公开了诸如涉及集成电路（IC）的互连布局的方法和装置。 一个这样的布局包括多个差分对线对。 每个差分对具有包括彼此基本平行地延伸的一个或多个平行部分的两条线。 每一对也包括屏蔽线。 每个屏蔽线包括插入在一对差动线之间的平行部分之间的一个或多个平行部分。 一个或多个屏蔽线电连接到电压基准，例如接地。 据信这种布局可以减少或消除对内耦合以及互对耦合。

公开(公告)号：US20100118632A1

公开(公告)日：2010-05-13

申请号：US12270533

申请日：2008-11-13

申请人： Yantao Ma ,  Todd Merritt

发明人： Yantao Ma ,  Todd Merritt

IPC分类号： G11C7/00 ,  G11C5/14

CPC分类号： G11C7/02 ,  G11C5/005 ,  G11C5/14 ,  G11C7/1027 ,  G11C11/406

摘要： Memory devices and methods are provided for reducing simultaneous switching output noise and power supply noise during burst data write and refresh operations. An embodiment of a memory device according to the present invention includes a first power domain coupled to some of the components of the memory device and a second power domain coupled to different components of the memory device. One or more distributed power domain coupling circuits may be coupled to the first and second power domains. The power domain coupling circuit includes a controller configured to generate an enable signal responsive to control signals, data signals, or any combination thereof. The power domain coupling circuit also includes coupling circuitry coupled to the first and second power domains and coupled to the controller. The coupling circuitry is configured to couple the first and second power domains together responsive to the enable signal.

摘要翻译： 提供存储器件和方法，用于在突发数据写入和刷新操作期间减少同时的开关输出噪声和电源噪声。 根据本发明的存储器件的实施例包括耦合到存储器件的一些部件的第一功率域和耦合到存储器件的不同部件的第二功率域。 一个或多个分布式电力域耦合电路可以耦合到第一和第二电力域。 功率域耦合电路包括响应于控制信号，数据信号或其任何组合来产生使能信号的控制器。 功率域耦合电路还包括耦合到第一和第二功率域并耦合到控制器的耦合电路。 耦合电路被配置为响应于使能信号将第一和第二功率域耦合到一起。

公开(公告)号：US20060248293A1

公开(公告)日：2006-11-02

申请号：US11456529

申请日：2006-07-10

申请人： Jeffrey Mailloux ,  Kevin Ryan ,  Todd Merritt ,  Brett Williams

发明人： Jeffrey Mailloux ,  Kevin Ryan ,  Todd Merritt ,  Brett Williams

IPC分类号： G06F13/00

CPC分类号： G11C7/1027 ,  G11C7/1015 ,  G11C7/1024 ,  G11C7/1039 ,  G11C7/1045 ,  G11C7/20

摘要： Apparatus and methods may operate to switch between burst modes and pipelined modes without using a WCBR (write and column address select before row address select) cycle, as well as to select an external address data path, instruct a memory to perform a desired memory operation, and perform the desired memory operation until terminated.

摘要翻译： 装置和方法可以操作以在突发模式和流水线模式之间切换，而不使用WCBR（行地址选择之前的写和列地址选择）周期，以及选择外部地址数据路径，指示存储器执行期望的存储器操作 ，并执行所需的存储器操作直到终止。

公开(公告)号：US6121822A

公开(公告)日：2000-09-19

申请号：US289177

申请日：1999-04-09

申请人： Todd Merritt

发明人： Todd Merritt

IPC分类号： H01L27/02 ,  G05F3/02

CPC分类号： H01L27/0222

摘要： Selected transistors in a charge pump circuit have their associated well regions tied to a capacitor electrode. As a result, the body effect in these devices is reduced, and, consequently, the threshold voltage is reduced as well. With a lower threshold voltage, these transistors allow the charge pump to quickly generate a voltage higher than the positive power supply voltage or a negative substrate bias voltage. In addition, the metal-insulator-semiconductor (MIS) capacitors in the charge pump preferably have their source/drain regions tied to an associated well region, thereby shorting the source/drain/well region junction. Thus, parasitic capacitances associated with these MIS capacitors is significantly reduced, further increasing the speed of the charge pump circuit.

摘要翻译： 电荷泵电路中的选定晶体管具有与电容器电极连接的相关联的阱区。 结果，这些装置中的身体效应被降低，因此阈值电压也降低。 利用较低的阈值电压，这些晶体管允许电荷泵快速产生高于正电源电压或负的衬底偏置电压的电压。 此外，电荷泵中的金属 - 绝缘体半导体（MIS）电容器优选地将其源极/漏极区域连接到相关联的阱区域，从而使源极/漏极/阱区域连接点短路。 因此，与这些MIS电容器相关联的寄生电容显着降低，进一步增加了电荷泵电路的速度。

公开(公告)号：US6072728A

公开(公告)日：2000-06-06

申请号：US915394

申请日：1997-08-20

申请人： Todd Merritt

发明人： Todd Merritt

IPC分类号： G11C11/417 ,  G11C7/10 ,  H03K19/0175 ,  H03K19/094 ,  H03K19/0948 ,  G11C11/40

CPC分类号： G11C7/1057 ,  G11C7/1051 ,  H03K19/09429

摘要： For use in a semiconductor circuit device, a uniquely-arranged tri-state output buffer responds to a control signal generated in the semiconductor circuit device and a below-ground voltage level at an output terminal to prevent wasted drain current and substrate current, and reduce capacitance at the pull-up node driving the output terminal. The output buffer includes a power supply signal providing at least one voltage level with respect to common; an output terminal; a pull-up node; a pull-down node; a first circuit responding to the control signal by providing a first control voltage on the pull-up node; and a second circuit responding to the control signal by providing a second control voltage on the pull-down node. Further, the output buffer includes a pull-up transistor, responsive to the voltage on the pull-up node and coupled between the power supply signal and the output terminal; a pull-down transistor, responsive to the voltage on the pull-down node and coupled between common and the output terminal; a bias circuit, responsive to a voltage level on the output terminal being at a level substantially below common, arranged to bias the pull-up node downwardly and away from the voltage level provided by the power supply signal; and a disable circuit, responsive to the voltage level on the output terminal being at a level substantially below common, constructed and arranged to disable the circuit providing the control voltage on the pull-up node. The pull-up transistor provides a high-level signal at the output terminal, the pull-down transistor provides a low-level signal at the output terminal, and the bias circuit in combination with the disable circuit respond to the voltage level on the output terminal being at a level substantially below common by preventing current flow from the power supply signal to the output terminal.

公开(公告)号：US5528173A

公开(公告)日：1996-06-18

申请号：US438645

申请日：1995-05-10

申请人： Todd Merritt ,  Troy Manning

发明人： Todd Merritt ,  Troy Manning

IPC分类号： H03K3/356 ,  H03K19/0175

CPC分类号： H03K3/356113 ,  H03K3/356017

摘要： A voltage level translator is disclosed which translates a CMOS input signal into a CMOS output signal where the low voltage level of the output signal is equal to the high voltage level of the input signal. The voltage level translator is described in an integrated circuit such as memory circuits, including DRAMs. Specifically, the voltage level translator produces an output signal which can be used as a gate voltage on a pre-charge transistor for a booted circuit where the gate voltage need only drop to the high voltage level of the input signal to shut the transistor off. The voltage level translator described, therefore, reduces the time and power required to translate an input signal by limiting the voltage swing of the output signal.

摘要翻译： 公开了一种电压电平转换器，其将CMOS输入信号转换成CMOS输出信号，其中输出信号的低电压电平等于输入信号的高电压电平。 在诸如包括DRAM的存储器电路的集成电路中描述了电压电平转换器。 具体地，电压电平转换器产生一个输出信号，该输出信号可以用作引导电路的预充电晶体管上的栅极电压，其中栅极电压只需要下降到输入信号的高电压电平以关闭晶体管。 因此，所描述的电压电平转换器通过限制输出信号的电压摆幅来减少转换输入信号所需的时间和功率。

公开(公告)号：US20110122720A1

公开(公告)日：2011-05-26

申请号：US13018702

申请日：2011-02-01

申请人： Yantao Ma ,  Todd Merritt

发明人： Yantao Ma ,  Todd Merritt

IPC分类号： G11C5/14

CPC分类号： G11C7/02 ,  G11C5/005 ,  G11C5/14 ,  G11C7/1027 ,  G11C11/406

摘要： Memory devices and methods are provided for reducing simultaneous switching output noise and power supply noise during burst data write and refresh operations. An embodiment of a memory device according to the present invention includes a first power domain coupled to some of the components of the memory device and a second power domain coupled to different components of the memory device. One or more distributed power domain coupling circuits may be coupled to the first and second power domains. The power domain coupling circuit includes a controller configured to generate an enable signal responsive to control signals, data signals, or any combination thereof. The power domain coupling circuit also includes coupling circuitry coupled to the first and second power domains and coupled to the controller. The coupling circuitry is configured to couple the first and second power domains together responsive to the enable signal.

摘要翻译： 提供存储器件和方法，用于在突发数据写入和刷新操作期间减少同时的开关输出噪声和电源噪声。 根据本发明的存储器件的实施例包括耦合到存储器件的一些部件的第一功率域和耦合到存储器件的不同部件的第二功率域。 一个或多个分布式电力域耦合电路可以耦合到第一和第二电力域。 功率域耦合电路包括响应于控制信号，数据信号或其任何组合来产生使能信号的控制器。 功率域耦合电路还包括耦合到第一和第二功率域并耦合到控制器的耦合电路。 耦合电路被配置为响应于使能信号将第一和第二功率域耦合到一起。

公开(公告)号：US07894285B2

公开(公告)日：2011-02-22

申请号：US12270533

申请日：2008-11-13

申请人： Yantao Ma ,  Todd Merritt

发明人： Yantao Ma ,  Todd Merritt

IPC分类号： G11C7/02

CPC分类号： G11C7/02 ,  G11C5/005 ,  G11C5/14 ,  G11C7/1027 ,  G11C11/406

摘要： Memory devices and methods are provided for reducing simultaneous switching output noise and power supply noise during burst data write and refresh operations. An embodiment of a memory device according to the present invention includes a first power domain coupled to some of the components of the memory device and a second power domain coupled to different components of the memory device. One or more distributed power domain coupling circuits may be coupled to the first and second power domains. The power domain coupling circuit includes a controller configured to generate an enable signal responsive to control signals, data signals, or any combination thereof. The power domain coupling circuit also includes coupling circuitry coupled to the first and second power domains and coupled to the controller. The coupling circuitry is configured to couple the first and second power domains together responsive to the enable signal.

摘要翻译： 提供存储器件和方法，用于在突发数据写入和刷新操作期间减少同时的开关输出噪声和电源噪声。 根据本发明的存储器件的实施例包括耦合到存储器件的一些部件的第一功率域和耦合到存储器件的不同部件的第二功率域。 一个或多个分布式电力域耦合电路可以耦合到第一和第二电力域。 功率域耦合电路包括响应于控制信号，数据信号或其任何组合来产生使能信号的控制器。 功率域耦合电路还包括耦合到第一和第二功率域并耦合到控制器的耦合电路。 耦合电路被配置为响应于使能信号将第一和第二功率域耦合到一起。