公开(公告)号：US08513087B2

公开(公告)日：2013-08-20

申请号：US13095019

申请日：2011-04-27

Applicant: Donald R. Disney ,  Richard K. Williams

Inventor： Donald R. Disney ,  Richard K. Williams

IPC: H01L21/76

CPC classification number: H01L21/76243 ,  H01L21/76267 ,  H01L21/763 ,  H01L21/823878 ,  H01L21/823892 ,  H01L29/1004 ,  H01L29/41708 ,  H01L29/732

Abstract: Processes for forming isolation structures for semiconductor devices include forming a submerged floor isolation region and a filed trench which together enclose an isolated pocket of the substrate. One process aligns the trench to the floor isolation region. In another process a second, narrower trench is formed in the isolated pocket and filled with a dielectric material while the dielectric material is deposited so as to line the walls and floor of the first trench. The substrate does not contain an epitaxial layer, thereby overcoming the many problems associated with fabricating the same.

Abstract translation: 用于形成用于半导体器件的隔离结构的工艺包括形成浸没的底部隔离区域和一起封装衬底的隔离袋状物的沟槽。 一个过程将沟槽对准地板隔离区域。 在另一种方法中，在隔离的袋中形成第二较窄的沟槽，并且填充介电材料，同时沉积电介质材料以便使第一沟槽的壁和底板成线。 衬底不含有外延层，从而克服了与其制造相关的许多问题。

公开(公告)号：US20100133611A1

公开(公告)日：2010-06-03

申请号：US12658020

申请日：2010-02-01

Applicant: Donald R. Disney ,  Richard K. Williams

Inventor： Donald R. Disney ,  Richard K. Williams

IPC: H01L29/78

CPC classification number: H01L29/0638 ,  H01L21/26586 ,  H01L29/0615 ,  H01L29/0626 ,  H01L29/063 ,  H01L29/0653 ,  H01L29/0661 ,  H01L29/086 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/41766 ,  H01L29/7809 ,  H01L29/7811 ,  H01L29/7835 ,  H01L29/808 ,  H01L29/8613 ,  H01L29/866 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A transistor is formed inside an isolation structure which includes a floor isolation region and a trench extending from the surface of the substrate to the floor isolation region. The trench may be filled with a dielectric material or may have a conductive material in a central portion with a dielectric layer lining the walls of the trench.

Abstract translation: 晶体管形成在隔离结构内，该隔离结构包括底板隔离区域和从衬底表面延伸到地板隔离区域的沟槽。 沟槽可以填充有介电材料，或者可以在中间部分具有导电材料，其中介电层衬在沟槽的壁上。

公开(公告)号：US20080230812A1

公开(公告)日：2008-09-25

申请号：US12072611

申请日：2008-02-27

Applicant: Donald R. Disney ,  Richard K. Williams

Inventor： Donald R. Disney ,  Richard K. Williams

IPC: H01L29/80

CPC classification number: H01L21/76243 ,  H01L21/26586 ,  H01L21/76267 ,  H01L21/763 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/098 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0626 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0661 ,  H01L29/086 ,  H01L29/10 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/41716 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/42316 ,  H01L29/732 ,  H01L29/7809 ,  H01L29/7811 ,  H01L29/7835 ,  H01L29/808 ,  H01L29/8613 ,  H01L29/866

Abstract: Various integrated circuit devices, in particular a junction field-effect transistor (JFET), are formed inside an isolation structure which includes a floor isolation region and a trench extending from the surface of the substrate to the floor isolation region. The trench may be filled with a dielectric material or may have a conductive material in a central portion with a dielectric layer lining the walls of the trench. Various techniques for terminating the isolation structure by extending the floor isolation region beyond the trench, using a guard ring, and a forming a drift region are described.

Abstract translation: 各种集成电路器件，特别是结型场效应晶体管（JFET）形成在隔离结构内部，该隔离结构包括底板隔离区域和从衬底表面延伸到地板隔离区域的沟槽。 沟槽可以填充有介电材料，或者可以在中间部分具有导电材料，其中介电层衬在沟槽的壁上。 描述了通过使用保护环将基底隔离区域延伸超过沟槽并形成漂移区域来终止隔离结构的各种技术。

公开(公告)号：US20080217729A1

公开(公告)日：2008-09-11

申请号：US12070035

申请日：2008-02-14

Applicant: Donald R. Disney ,  Richard K. Williams

Inventor： Donald R. Disney ,  Richard K. Williams

IPC: H01L29/00

CPC classification number: H01L21/76243 ,  H01L21/76267 ,  H01L21/763 ,  H01L21/8222 ,  H01L21/82285 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0825 ,  H01L27/0826 ,  H01L29/1004 ,  H01L29/41708 ,  H01L29/732

Abstract: An isolated CMOS pair of transistors formed in a P-type semiconductor substrate includes an N-type submerged floor isolation region and a filled trench extending downward from the surface of the substrate to the floor isolation region. Together the floor isolation region and the filled trench form an isolated pocket of the substrate which contains a P-channel MOSFET in an N-well and an N-channel MOSFET in a P-well. The substrate does not contain an epitaxial layer, thereby overcoming the many problems associated with fabricating the same.

Abstract translation: 形成在P型半导体衬底中的隔离的CMOS对晶体管包括N型浸没层隔离区和从衬底表面向底部隔离区向下延伸的填充沟槽。 底部隔离区域和填充沟槽一起形成衬底的隔离袋，其在N阱中包含P沟道MOSFET，在P阱中包含N沟道MOSFET。 衬底不含有外延层，从而克服了与其制造相关的许多问题。

公开(公告)号：US20080210980A1

公开(公告)日：2008-09-04

申请号：US12069941

申请日：2008-02-14

Applicant: Donald R. Disney ,  Richard K. Williams

Inventor： Donald R. Disney ,  Richard K. Williams

IPC: H01L27/092

CPC classification number: H01L21/761 ,  H01L21/76243 ,  H01L21/76267 ,  H01L21/763 ,  H01L21/8222 ,  H01L21/82285 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0825 ,  H01L27/0826 ,  H01L29/41708 ,  H01L29/732

Abstract: Isolated CMOS transistors formed in a P-type semiconductor substrate include an N-type submerged floor isolation region and a filled trench extending downward from the surface of the substrate to the floor isolation region. Together the floor isolation region and the filled trench form an isolated pocket of the substrate which contains a P-channel MOSFET in an N-well and an N-channel MOSFET in a P-well. The substrate does not contain an epitaxial layer, thereby overcoming the many problems associated with fabricating the same.

Abstract translation: 形成在P型半导体衬底中的隔离CMOS晶体管包括N型浸没式地板隔离区域和从衬底表面向底部隔离区域向下延伸的填充沟槽。 底部隔离区域和填充沟槽一起形成衬底的隔离袋，其在N阱中包含P沟道MOSFET，在P阱中包含N沟道MOSFET。 衬底不含有外延层，从而克服了与其制造相关的许多问题。

公开(公告)号：US20080197445A1

公开(公告)日：2008-08-21

申请号：US12072612

申请日：2008-02-27

Applicant: Donald R. Disney ,  Richard K. Williams

Inventor： Donald R. Disney ,  Richard K. Williams

IPC: H01L23/58

CPC classification number: H01L29/7835 ,  H01L21/76264 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0626 ,  H01L29/063 ,  H01L29/0638 ,  H01L29/0661 ,  H01L29/086 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/41766 ,  H01L29/7809 ,  H01L29/7811 ,  H01L29/808 ,  H01L29/8613 ,  H01L29/866 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Various integrated circuit devices, including a lateral DMOS transistor, a quasi-vertical DMOS transistor, a junction field-effect transistor (JFET), a depletion-mode MOSFET, and a diode, are formed inside an isolation structure which includes a floor isolation region and a trench extending from the surface of the substrate to the floor isolation region. The trench may be filled with a dielectric material or may have a conductive material in a central portion with a dielectric layer lining the walls of the trench. Various techniques for terminating the isolation structure by extending the floor isolation region beyond the trench, using a guard ring, and a forming a drift region are described.

Abstract translation: 包括横向DMOS晶体管，准垂直DMOS晶体管，结型场效应晶体管（JFET），耗尽型MOSFET和二极管的各种集成电路器件形成在隔离结构内，隔离结构包括地板隔离区域 以及从衬底的表面延伸到地板隔离区的沟槽。 沟槽可以填充有介电材料，或者可以在中间部分具有导电材料，其中介电层衬在沟槽的壁上。 描述了通过使用保护环将基底隔离区域延伸超过沟槽并形成漂移区域来终止隔离结构的各种技术。

公开(公告)号：US08659116B2

公开(公告)日：2014-02-25

申请号：US12658020

申请日：2010-02-01

Applicant: Donald R. Disney ,  Richard K. Williams

Inventor： Donald R. Disney ,  Richard K. Williams

IPC: H01L21/70

CPC classification number: H01L29/0638 ,  H01L21/26586 ,  H01L29/0615 ,  H01L29/0626 ,  H01L29/063 ,  H01L29/0653 ,  H01L29/0661 ,  H01L29/086 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/41766 ,  H01L29/7809 ,  H01L29/7811 ,  H01L29/7835 ,  H01L29/808 ,  H01L29/8613 ,  H01L29/866 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A transistor is formed inside an isolation structure which includes a floor isolation region and a trench extending from the surface of the substrate to the floor isolation region. The trench may be filled with a dielectric material or may have a conductive material in a central portion with a dielectric layer lining the walls of the trench.

公开(公告)号：US08089129B2

公开(公告)日：2012-01-03

申请号：US12069941

申请日：2008-02-14

Applicant: Donald R. Disney ,  Richard K. Williams

Inventor： Donald R. Disney ,  Richard K. Williams

IPC: H01L21/70

CPC classification number: H01L21/761 ,  H01L21/76243 ,  H01L21/76267 ,  H01L21/763 ,  H01L21/8222 ,  H01L21/82285 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0825 ,  H01L27/0826 ,  H01L29/41708 ,  H01L29/732

Abstract: Isolated CMOS transistors formed in a P-type semiconductor substrate include an N-type submerged floor isolation region and a filled trench extending downward from the surface of the substrate to the floor isolation region. Together the floor isolation region and the filled trench form an isolated pocket of the substrate which contains a P-channel MOSFET in an N-well and an N-channel MOSFET in a P-well. The substrate does not contain an epitaxial layer, thereby overcoming the many problems associated with fabricating the same.

Abstract translation: 形成在P型半导体衬底中的隔离CMOS晶体管包括N型浸没式地板隔离区域和从衬底表面向底部隔离区域向下延伸的填充沟槽。 底部隔离区域和填充沟槽一起形成衬底的隔离袋，其在N阱中包含P沟道MOSFET，在P阱中包含N沟道MOSFET。 衬底不含有外延层，从而克服了与其制造相关的许多问题。

公开(公告)号：US20110201171A1

公开(公告)日：2011-08-18

申请号：US13095019

申请日：2011-04-27

Applicant: Donald R. Disney ,  Richard K. Williams

Inventor： Donald R. Disney ,  Richard K. Williams

IPC: H01L21/762

CPC classification number: H01L21/76243 ,  H01L21/76267 ,  H01L21/763 ,  H01L21/823878 ,  H01L21/823892 ,  H01L29/1004 ,  H01L29/41708 ,  H01L29/732

Abstract: Processes for forming isolation structures for semiconductor devices include forming a submerged floor isolation region and a filed trench which together enclose an isolated pocket of the substrate. One process aligns the trench to the floor isolation region. In another process a second, narrower trench is formed in the isolated pocket and filled with a dielectric material while the dielectric material is deposited so as to line the walls and floor of the first trench. The substrate does not contain an epitaxial layer, thereby overcoming the many problems associated with fabricating the same.

Abstract translation: 用于形成用于半导体器件的隔离结构的工艺包括形成浸没的底部隔离区域和一起封装衬底的隔离袋状物的沟槽。 一个过程将沟槽对准地板隔离区域。 在另一种方法中，在隔离的袋中形成第二较窄的沟槽，并且填充介电材料，同时沉积电介质材料以便使第一沟槽的壁和底板成线。 衬底不含有外延层，从而克服了与其制造相关的许多问题。

公开(公告)号：US20080213972A1

公开(公告)日：2008-09-04

申请号：US12070036

申请日：2008-02-14

Applicant: Donald R. Disney ,  Richard K. Williams

Inventor： Donald R. Disney ,  Richard K. Williams

IPC: H01L21/762

CPC classification number: H01L21/76243 ,  H01L21/761 ,  H01L21/76267 ,  H01L21/763 ,  H01L21/8222 ,  H01L21/82285 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0825 ,  H01L27/0826 ,  H01L29/1004 ,  H01L29/41708 ,  H01L29/732

Abstract: Processes for forming isolation structures for semiconductor devices include forming a submerged floor isolation region and a filed trench which together enclose an isolated pocket of the substrate. One process aligns the trench to the floor isolation region. In another process a second, narrower trench is formed in the isolated pocket and filled with a dielectric material while the dielectric material is deposited so as to line the walls and floor of the first trench. The substrate does not contain an epitaxial layer, thereby overcoming the many problems associated with fabricating the same.

Abstract translation: 用于形成用于半导体器件的隔离结构的工艺包括形成浸没的底部隔离区域和一起封装衬底的隔离袋状物的沟槽。 一个过程将沟槽对准地板隔离区域。 在另一种方法中，在隔离的袋中形成第二较窄的沟槽，并且填充介电材料，同时沉积电介质材料以便使第一沟槽的壁和底板成线。 衬底不含有外延层，从而克服了与其制造相关的许多问题。