公开(公告)号：US08822311B2

公开(公告)日：2014-09-02

申请号：US13335329

申请日：2011-12-22

申请人： Isik C. Kizilyalli ,  Hui Nie ,  Andrew P. Edwards ,  Richard J. Brown ,  Donald R. Disney

发明人： Isik C. Kizilyalli ,  Hui Nie ,  Andrew P. Edwards ,  Richard J. Brown ,  Donald R. Disney

IPC分类号： H01L29/20 ,  H01L29/24

CPC分类号： H01L29/868 ,  H01L29/0615 ,  H01L29/0649 ,  H01L29/2003 ,  H01L29/66204 ,  H01L29/66212 ,  H01L29/6631 ,  H01L29/66924

摘要： A III-nitride semiconductor device includes an active region for supporting current flow during forward-biased operation of the III-nitride semiconductor device. The active region includes a first III-nitride epitaxial material having a first conductivity type, and a second III-nitride epitaxial material having a second conductivity type. The III-nitride semiconductor device further includes an edge-termination region physically adjacent to the active region and including an implanted region comprising a portion of the first III-nitride epitaxial material. The implanted region of the first III-nitride epitaxial material has a reduced electrical conductivity in relation to portions of the first III-nitride epitaxial material adjacent to the implanted region.

摘要翻译： III族氮化物半导体器件包括用于在III族氮化物半导体器件的正向偏置操作期间支持电流的有源区域。 有源区包括具有第一导电类型的第一III族氮化物外延材料和具有第二导电类型的第二III族氮化物外延材料。 III族氮化物半导体器件还包括物理地邻近有源区的边缘终端区，并且包括包含第一III族氮化物外延材料的一部分的注入区。 第一III族氮化物外延材料的注入区域相对于与注入区域相邻的第一III族氮化物外延材料的部分具有降低的导电性。

公开(公告)号：US08785975B2

公开(公告)日：2014-07-22

申请号：US13529822

申请日：2012-06-21

申请人： Hui Nie ,  Andrew P. Edwards ,  Donald R. Disney ,  Isik C. Kizilyalli

发明人： Hui Nie ,  Andrew P. Edwards ,  Donald R. Disney ,  Isik C. Kizilyalli

IPC分类号： H01L27/088 ,  H01L29/778 ,  H01L29/06

CPC分类号： H01L21/0254 ,  H01L21/02664 ,  H01L21/8252 ,  H01L27/0605 ,  H01L29/0657 ,  H01L29/7786 ,  Y10S438/978

摘要： A semiconductor device includes a III-nitride substrate of a first conductivity type, a first III-nitride epitaxial layer of the first conductivity type coupled to the III-nitride substrate, and a first III-nitride epitaxial structure coupled to a first portion of a surface of the first III-nitride epitaxial layer. The first III-nitride epitaxial structure has a sidewall. The semiconductor device further includes a second III-nitride epitaxial structure of the first conductivity type coupled to the first III-nitride epitaxial structure, a second III-nitride epitaxial layer of the first conductivity type coupled to the sidewall of the second III-nitride epitaxial layer and a second portion of the surface of the first III-nitride epitaxial layer, and a third III-nitride epitaxial layer of a second conductivity type coupled to the second III-nitride epitaxial layer. The semiconductor device also includes one or more dielectric structures coupled to a surface of the third III-nitride epitaxial layer.

摘要翻译： 半导体器件包括第一导电类型的III族氮化物衬底，耦合到III族氮化物衬底的第一导电类型的第一III族氮化物外延层和耦合到第一III族氮化物外延结构的第一部分 第一III族氮化物外延层的表面。 第一III族氮化物外延结构具有侧壁。 半导体器件还包括耦合到第一III族氮化物外延结构的第一导电类型的第二III族氮化物外延结构，第一导电类型的第二III族氮化物外延层耦合到第二III族氮化物外延的侧壁 层和第一III族氮化物外延层的表面的第二部分，以及耦合到第二III族氮化物外延层的第二导电类型的第三III族氮化物外延层。 半导体器件还包括耦合到第三III族氮化物外延层的表面的一个或多个电介质结构。

公开(公告)号：US20140042447A1

公开(公告)日：2014-02-13

申请号：US13572408

申请日：2012-08-10

申请人： Hui Nie ,  Donald R. Disney ,  Isik C. Kizilyalli

发明人： Hui Nie ,  Donald R. Disney ,  Isik C. Kizilyalli

IPC分类号： H01L29/80 ,  H01L29/20 ,  H01L21/20

CPC分类号： H01L21/0254 ,  H01L21/02645 ,  H01L21/6835 ,  H01L24/83 ,  H01L29/2003 ,  H01L29/66204 ,  H01L29/66212 ,  H01L29/66356 ,  H01L29/66446 ,  H01L29/739 ,  H01L29/8083 ,  H01L29/861 ,  H01L29/872 ,  H01L2221/68327 ,  H01L2224/04026 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/32245 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2924/12032 ,  H01L2924/13062 ,  H01L2924/00014 ,  H01L2924/00

摘要： A method for fabricating an electronic device includes providing an engineered substrate structure comprising a III-nitride seed layer, forming GaN-based functional layers coupled to the III-nitride seed layer, and forming a first electrode structure electrically coupled to at least a portion of the GaN-based functional layers. The method also includes joining a carrier substrate opposing the GaN-based functional layers and removing at least a portion of the engineered substrate structure. The method further includes forming a second electrode structure electrically coupled to at least another portion of the GaN-based functional layers and removing the carrier substrate.

摘要翻译： 一种制造电子器件的方法包括提供包括III族氮化物种子层的工程化衬底结构，形成与III族氮化物种子层耦合的GaN基功能层，以及形成电耦合到至少一部分 GaN基功能层。 该方法还包括将与GaN基功能层相对的载体衬底接合并去除工程衬底结构的至少一部分。 该方法还包括形成电耦合到GaN基功能层的至少另一部分并去除载体衬底的第二电极结构。

公开(公告)号：US20130341677A1

公开(公告)日：2013-12-26

申请号：US13529822

申请日：2012-06-21

申请人： Hui Nie ,  Donald R. Disney ,  Andrew P. Edwards ,  Isik C. Kizilyalli

发明人： Hui Nie ,  Donald R. Disney ,  Andrew P. Edwards ,  Isik C. Kizilyalli

IPC分类号： H01L27/088 ,  H01L21/8234

CPC分类号： H01L21/0254 ,  H01L21/02664 ,  H01L21/8252 ,  H01L27/0605 ,  H01L29/0657 ,  H01L29/7786 ,  Y10S438/978

摘要： A semiconductor device includes a III-nitride substrate of a first conductivity type, a first III-nitride epitaxial layer of the first conductivity type coupled to the III-nitride substrate, and a first III-nitride epitaxial structure coupled to a first portion of a surface of the first III-nitride epitaxial layer. The first III-nitride epitaxial structure has a sidewall. The semiconductor device further includes a second III-nitride epitaxial structure of the first conductivity type coupled to the first III-nitride epitaxial structure, a second III-nitride epitaxial layer of the first conductivity type coupled to the sidewall of the second III-nitride epitaxial layer and a second portion of the surface of the first III-nitride epitaxial layer, and a third III-nitride epitaxial layer of a second conductivity type coupled to the second III-nitride epitaxial layer. The semiconductor device also includes one or more dielectric structures coupled to a surface of the third III-nitride epitaxial layer.

摘要翻译： 半导体器件包括第一导电类型的III族氮化物衬底，耦合到III族氮化物衬底的第一导电类型的第一III族氮化物外延层和耦合到第一III族氮化物外延结构的第一部分 第一III族氮化物外延层的表面。 第一III族氮化物外延结构具有侧壁。 半导体器件还包括耦合到第一III族氮化物外延结构的第一导电类型的第二III族氮化物外延结构，第一导电类型的第二III族氮化物外延层耦合到第二III族氮化物外延的侧壁 层和第一III族氮化物外延层的表面的第二部分，以及耦合到第二III族氮化物外延层的第二导电类型的第三III族氮化物外延层。 半导体器件还包括耦合到第三III族氮化物外延层的表面的一个或多个电介质结构。

公开(公告)号：US08541987B2

公开(公告)日：2013-09-24

申请号：US12956351

申请日：2010-11-30

申请人： Donald R. Disney ,  Michael Hsing ,  James Nguyen ,  James Moyer

发明人： Donald R. Disney ,  Michael Hsing ,  James Nguyen ,  James Moyer

IPC分类号： H02J7/00 ,  H02J7/04

CPC分类号： H02M1/44 ,  H02M1/32 ,  H02M2001/322

摘要： A discharge circuit for an EMI filter capacitor includes normally-ON transistors. The normally-ON transistors may be controlled to limit current through them when an AC source is coupled across the discharge circuit. When the AC source is disconnected from the discharge circuit, the normally-ON transistors turn ON to allow current flow through them. The current flow allows the EMI filter capacitor to be discharged by a discharge resistor.

摘要翻译： 用于EMI滤波电容器的放电电路包括常开晶体管。 当AC源耦合在放电电路两端时，可以控制常ON晶体管以限制通过它们的电流。 当交流电源与放电电路断开连接时，常开晶体管导通，允许电流流过它们。 电流流过允许EMI滤波电容通过放电电阻放电。

公开(公告)号：US20120320476A1

公开(公告)日：2012-12-20

申请号：US13162512

申请日：2011-06-16

申请人： Donald R. Disney

发明人： Donald R. Disney

IPC分类号： H02H9/04 ,  H01L27/06

CPC分类号： H03K17/0822

摘要： The present technology discloses a high-voltage device comprising a high-voltage transistor and an integrated over-voltage protection circuit. The over-voltage protection circuit monitors a voltage across the high-voltage transistor to detect an over-voltage condition of the high-voltage transistor, and turns the high-voltage transistor ON when the over-voltage condition is detected. Thus, once the high-voltage transistor is in over-voltage condition, the high-voltage transistor is turned ON and can dissipate the power from the over-voltage event through its channel.

摘要翻译： 本技术公开了一种包括高压晶体管和集成过电压保护电路的高压装置。 过电压保护电路监视高电压晶体管两端的电压，以检测高电压晶体管的过压状态，并在检测到过电压状态时将高电压晶体管导通。 因此，一旦高电压晶体管处于过电压状态，高压晶体管导通，并可通过其通道从过电压事件中消耗功率。

公开(公告)号：US20120280308A1

公开(公告)日：2012-11-08

申请号：US13099252

申请日：2011-05-02

申请人： Donald R. Disney

发明人： Donald R. Disney

IPC分类号： H01L29/772 ,  H01L21/60

CPC分类号： H01L23/49575 ,  H01L21/823487 ,  H01L23/3121 ,  H01L23/49562 ,  H01L24/16 ,  H01L24/48 ,  H01L24/49 ,  H01L27/0688 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49109 ,  H01L2224/73257 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/12032 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： The present technology is directed generally to a semiconductor device. In one embodiment, the semiconductor device includes a first vertical transistor and a second vertical transistor, and the first vertical transistor is stacked on top of the second vertical transistor. The first vertical transistor is mounted on a lead frame with the source electrode of the first vertical transistor coupled to the lead frame. The second vertical transistor is stacked on the first vertical transistor with the source electrode of the second vertical transistor coupled to the drain electrode of the first vertical transistor.

摘要翻译： 本技术通常涉及半导体器件。 在一个实施例中，半导体器件包括第一垂直晶体管和第二垂直晶体管，并且第一垂直晶体管堆叠在第二垂直晶体管的顶部上。 第一垂直晶体管安装在引线框架上，第一垂直晶体管的源电极耦合到引线框架。 第二垂直晶体管堆叠在第一垂直晶体管上，其中第二垂直晶体管的源极耦合到第一垂直晶体管的漏极。

公开(公告)号：US08264858B2

公开(公告)日：2012-09-11

申请号：US13399755

申请日：2012-02-17

申请人： Donald R. Disney

发明人： Donald R. Disney

IPC分类号： H02M3/335

CPC分类号： H01L29/7803 ,  G05F1/14 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/7802 ,  H01L29/7813 ,  H02M1/36 ,  H02M3/335 ,  H02M3/33507 ,  H02M3/33553 ,  H02M3/33561 ,  H02M2001/0009

摘要： A technique for controlling a power supply with power supply control element with a tap element. An example power supply control element includes a power transistor that has first and second main terminals, a control terminal and a tap terminal. A control circuit is coupled to the control terminal. The tap terminal and the second main terminal of the power transistor are to control switching of the power transistor. The tap terminal is coupled to provide a signal to the control circuit substantially proportional to a voltage between the first and second main terminals when the voltage is less than a pinch off voltage. The tap terminal is coupled to provide a substantially constant voltage that is less than the voltage between the first and second main terminals to the control circuit when the voltage between the first and second main terminals is greater than the pinch-off voltage.

摘要翻译： 一种用电源控制元件与抽头元件控制电源的技术。 示例性电源控制元件包括具有第一和第二主端子的功率晶体管，控制端子和抽头端子。 控制电路耦合到控制终端。 功率晶体管的抽头端子和第二主端子用于控制功率晶体管的开关。 当电压小于夹断电压时，抽头端子被耦合以向控制电路提供基本上与第一和第二主端子之间的电压成比例的信号。 当第一和第二主端子之间的电压大于夹断电压时，抽头端子被耦合以提供小于控制电路的第一和第二主端子之间的电压的基本恒定的电压。

公开(公告)号：US20120139012A1

公开(公告)日：2012-06-07

申请号：US13365081

申请日：2012-02-02

申请人： Donald R. Disney

发明人： Donald R. Disney

IPC分类号： H01L29/808

CPC分类号： H02M1/36 ,  H01L21/823493 ,  H01L27/088 ,  H01L29/0634 ,  H01L29/1066 ,  H01L29/1075 ,  H01L29/1087 ,  H01L29/402 ,  H01L29/7835 ,  H01L29/808 ,  H02M3/33507 ,  H03K17/0822

摘要： A high-voltage junction field-effect transistor (JFET) includes a semiconductor substrate, a well region, first, second, and third doped regions, and first, second, and third terminals. The first doped region is disposed in the well region and the second dope region is laterally displaced from the well region. The third doped region is disposed in the well region between the first and second doped regions. A portion of the well region is substantially depleted of free charge carriers when a first voltage between the first and second terminals is greater than or equal to a pinch-off voltage. A voltage output at the third terminal is substantially proportional to the first voltage when the first voltage is less than the pinch-off voltage, and the voltage output at the third terminal is substantially fixed and less than the first voltage when the first voltage is greater than or equal to the pinch-off voltage.

摘要翻译： 高压结场效应晶体管（JFET）包括半导体衬底，阱区，第一，第二和第三掺杂区以及第一，第二和第三端。 第一掺杂区域设置在阱区域中，并且第二掺杂区域从阱区域横向移位。 第三掺杂区域设置在第一和第二掺杂区域之间的阱区域中。 当第一和第二端子之间的第一电压大于或等于夹断电压时，阱区的一部分基本上耗尽自由电荷载体。 当第一电压小于夹断电压时，第三端子处的电压输出基本上与第一电压成比例，并且第三端子处的电压输出基本上固定，并且当第一电压较大时小于第一电压 大于或等于夹断电压。

公开(公告)号：US20120126340A1

公开(公告)日：2012-05-24

申请号：US12949272

申请日：2010-11-18

申请人： Donald R. DISNEY

发明人： Donald R. DISNEY

IPC分类号： H01L29/772 ,  H01L21/336

CPC分类号： H01L29/7833 ,  H01L21/2652 ,  H01L29/1083 ,  H01L29/6659

摘要： An MOS transistor includes a doping profile that selectively increases the dopant concentration of the body region. The doping profile has a shallow portion that increases the dopant concentration of the body region just under the surface of the transistor under the gate, and a deep portion that increases the dopant concentration of the body region under the source and drain regions. The doping profile may be formed by implanting dopants through the gate, source region, and drain region. The dopants may be implanted in a high energy ion implant step through openings of a mask that is also used to perform another implant step. The dopants may also be implanted through openings of a dedicated mask.

摘要翻译： MOS晶体管包括选择性地增加身体区域的掺杂剂浓度的掺杂分布。 掺杂分布具有浅部分，其增加正好在栅极下的晶体管的表面下方的体区的掺杂剂浓度，以及增加源极和漏极区下的体区的掺杂剂浓度的深部。 可以通过在栅极，源极区和漏极区注入掺杂剂来形成掺杂分布。 掺杂剂可以通过掩模的开口在高能离子注入步骤中植入，掩模的开口也用于执行另一个注入步骤。 掺杂剂也可以通过专用掩模的开口植入。