METHOD FOR GROWING ZIRCONIUM NITRIDE CRYSTAL
    3.
    发明申请
    METHOD FOR GROWING ZIRCONIUM NITRIDE CRYSTAL 审中-公开
    生长氮化锆晶体的方法

    公开(公告)号:US20150225874A1

    公开(公告)日:2015-08-13

    申请号:US14422562

    申请日:2012-08-21

    申请人: Sung Moo Kim

    发明人: Sung Moo Kim

    IPC分类号: C30B25/02 C30B29/38

    摘要: According to the present invention, if a zirconium nitride lattice is grown by a method for growing zirconium nitride using a metal-organic vapor phase epitaxy method, the lattice binding efficiency of ZrN and GaN can enable a low cost preparation of an LED having high performance and it is very advantageous to grow a green LED by a direct band gap in the presence of Zr3N4. In addition, InZr3N4 can be substituted for In when growing a MQW in an LED, and thus it is very advantageous to prepare green and red LEDs. Further, a more satisfactory diffusion current can be obtained using ZrN or Zr3N4 as an epitaxial interlayer, and thus it is very advantageous in the application of a large LED chip and it is possible to prevent thermal expansion or cracks with respect to a silicon substrate.

    摘要翻译: 根据本发明,如果通过使用金属 - 有机气相外延法的生长氮化锆的方法生长氮化锆晶格,则ZrN和GaN的晶格结合效率可以使得具有高性能的LED的低成本准备 并且在Zr 3 N 4存在下通过直接带隙生长绿色LED是非常有利的。 另外,当在LED中生长MQW时,InZr3N4可以代替In,因此制备绿色和红色LED是非常有利的。 此外,可以使用ZrN或Zr3N4作为外延中间层获得更令人满意的扩散电流,因此在应用大的LED芯片方面是非常有利的,并且可以防止相对于硅衬底的热膨胀或裂纹。

    Well photoresist pattern of semiconductor device and method for forming the same
    4.
    发明授权
    Well photoresist pattern of semiconductor device and method for forming the same 失效
    半导体器件的良好的光致抗蚀剂图案及其形成方法

    公开(公告)号:US07488672B2

    公开(公告)日:2009-02-10

    申请号:US11493379

    申请日:2006-07-25

    申请人: Sung Moo Kim

    发明人: Sung Moo Kim

    IPC分类号: H01L21/425

    摘要: Disclosed is a well photoresist pattern of a semiconductor, and the fabrication method thereof. The method includes the steps of: (a) forming a sacrificial oxide layer on a semiconductor substrate; (b) applying a primer on the sacrificial oxide layer; (c) applying a photoresist on the primer; (d) soft-baking the photoresist; (e) exposing the photoresist to light by defocusing the DOF (depth of focus) of the light transmitted to the substrate; (f) post exposure baking the photoresist; (g) developing the photo-exposed photoresist to form a well photoresist pattern; and (h) hard-baking the well photoresist pattern. It is preferable that the exposure is performed by plus(+) defocusing of light.

    摘要翻译: 公开了半导体的良好的光致抗蚀剂图案及其制造方法。 该方法包括以下步骤:(a)在半导体衬底上形成牺牲氧化物层; (b)在所述牺牲氧化物层上施加底漆; (c)在底漆上施加光致抗蚀剂; (d)软化光刻胶; (e)通过使透射到衬底的光的DOF(焦深)散焦而使光致抗蚀剂曝光; (f)曝光后烘烤光刻胶; (g)显影曝光的光致抗蚀剂以形成良好的光致抗蚀剂图案; 和(h)硬烘烤光致抗蚀剂图案。 优选的是,通过加(+)光的散焦进行曝光。

    Method for manufacturing CMOS image sensor
    5.
    发明授权
    Method for manufacturing CMOS image sensor 失效
    CMOS图像传感器的制造方法

    公开(公告)号:US07659133B2

    公开(公告)日:2010-02-09

    申请号:US11646096

    申请日:2006-12-26

    申请人: Sung Moo Kim

    发明人: Sung Moo Kim

    IPC分类号: H01L21/00 H01L21/8238

    摘要: Disclosed is a method for manufacturing a CMOS image sensor, capable of preventing dopants implanted with high energy from penetrating into a lower part of a gate electrode when a photodiode is formed, thereby preventing current leakage of a transistor and variation of a threshold voltage. The method includes the steps of forming a gate electrode on a transistor area of a first conductive type semiconductor substrate including a photodiode area and the transistor area, forming a salicide layer on the gate electrode, and implanting second conductive type dopants for forming a photodiode in a photodiode area of the semiconductor substrate.

    摘要翻译: 公开了一种制造CMOS图像传感器的方法,当形成光电二极管时,能够防止注入高能量的掺杂剂渗透到栅电极的下部,从而防止晶体管的电流泄漏和阈值电压的变化。 该方法包括以下步骤:在包括光电二极管区域和晶体管区域的第一导电类型半导体衬底的晶体管区域上形成栅电极,在栅电极上形成自对准硅化物层,以及将用于形成光电二极管的第二导电型掺杂剂注入 半导体衬底的光电二极管区域。

    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
    6.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
    半导体器件及其制造方法

    公开(公告)号:US20070155078A1

    公开(公告)日:2007-07-05

    申请号:US11614697

    申请日:2006-12-21

    摘要: A semiconductor device including at least one of: lightly doped drain regions over a semiconductor substrate; a gate insulating layer over a semiconductor substrate between lightly doped drain regions; and/or a gate formed at an upper side of a gate insulating layer. A lower width of a gate may be less than an interval between lightly doped drain regions. An upper width of a gate may be greater than an interval between lightly doped drain regions.

    摘要翻译: 一种半导体器件,包括半导体衬底上的轻掺杂漏极区中的至少一个; 在轻掺杂漏区之间的半导体衬底上的栅极绝缘层; 和/或形成在栅极绝缘层的上侧的栅极。 栅极的较低宽度可以小于轻掺杂漏极区之间的间隔。 栅极的上部宽度可以大于轻掺杂漏极区域之间的间隔。