公开(公告)号：US12100774B2

公开(公告)日：2024-09-24

申请号：US17878348

申请日：2022-08-01

Applicant: The Boeing Company

Inventor： Eric Rehder ,  Philip Chiu ,  Tom Crocker ,  Daniel Law ,  Dale Waterman

IPC: H01L31/042 ,  H01L21/02 ,  H01L27/142 ,  H01L31/02 ,  H01L31/0224 ,  H01L31/0352 ,  H01L31/0392 ,  H01L31/044 ,  H01L31/0443 ,  H01L31/048 ,  H01L31/05 ,  H01L31/0687 ,  H02S40/34

CPC classification number: H01L31/042 ,  H01L21/02439 ,  H01L27/142 ,  H01L31/02 ,  H01L31/02008 ,  H01L31/02021 ,  H01L31/022425 ,  H01L31/035281 ,  H01L31/03529 ,  H01L31/0392 ,  H01L31/044 ,  H01L31/0443 ,  H01L31/048 ,  H01L31/05 ,  H01L31/0504 ,  H01L31/0508 ,  H01L31/0516 ,  H01L31/0687 ,  H02S40/34 ,  Y02E10/544

Abstract: A solar cell for a solar cell array with one or more grid on a surface thereof, wherein electrical connections are made to the grids in a plurality of locations positioned around the solar cell; and the electrical connections extend to one or more conductors located under the solar cell. The conductors located under the solar cell are buried within a substrate, and each of the conductors comprises a low resistance conducting path that distributes current from the solar cell. The conductors are loops, U-shaped, or have only up or down pathways. The solar cell comprises a full cell that has four cropped corners and the locations are in the cropped corners.

公开(公告)号：US20240154021A1

公开(公告)日：2024-05-09

申请号：US18090875

申请日：2022-12-29

Applicant: NATIONAL SUN YAT-SEN UNIVERSITY

Inventor： TING-CHANG CHANG ,  Wei-Chen Huang ,  Shih-Kai Lin ,  Yong-Ci Zhang ,  Sheng-Yao Chou ,  Chung-Wei Wu ,  Po-Hsun Chen

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/20 ,  H01L29/778

CPC classification number: H01L29/66462 ,  H01L21/0228 ,  H01L21/02439 ,  H01L21/02521 ,  H01L29/2003 ,  H01L29/7786

Abstract: A p-GaN high-electron-mobility transistor (HEMT) includes a buffer layer stacked on a substrate, a channel layer stacked on the buffer layer, a supply layer stacked on the channel layer, a doped layer stacked on the supply layer, and a hydrogen barrier layer covering the supply layer and the doped layer. A source and a drain are electrically connected to the channel layer and the supply layer, respectively. A gate is located on the doped layer. The hydrogen barrier layer is doped with fluorine.

公开(公告)号：US20230207307A1

公开(公告)日：2023-06-29

申请号：US17906733

申请日：2021-04-01

Applicant: SHIN-ETSU CHEMICAL CO., LTD.

Inventor： Shoji AKIYAMA

IPC: H01L21/02 ,  H01L21/225 ,  H01L21/304 ,  H01L21/762 ,  H01L23/00

CPC classification number: H01L21/02123 ,  H01L21/02255 ,  H01L21/02439 ,  H01L21/2253 ,  H01L21/304 ,  H01L21/76262 ,  H01L24/05 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2924/1068 ,  C30B29/30

Abstract: Provided are a composite substrate in which a wafer to be bonded has a sufficiently small surface roughness and which can be prevented from causing film peeling, and a method for producing the composite substrate. The composite substrate 40 of the present invention has a silicon wafer 10, an interlayer 11, and a single-crystal silicon thin film or oxide single-crystal thin film 20a stacked in the order listed and has a damaged layer 12a in a portion of the silicon wafer 10 on the side of the interlayer 11.

公开(公告)号：US10038115B2

公开(公告)日：2018-07-31

申请号：US15634583

申请日：2017-06-27

Applicant: GLO AB

Inventor： Carl Patrik Theodor Svensson ,  Nathan Gardner

IPC: H01L21/00 ,  H01L33/00 ,  H01L33/24 ,  H01L33/16 ,  H01L21/02 ,  H01L33/06 ,  H01L33/44 ,  B82Y20/00 ,  H01L33/08

CPC classification number: H01L33/0075 ,  B82Y20/00 ,  H01L21/0237 ,  H01L21/02439 ,  H01L21/02458 ,  H01L21/02505 ,  H01L21/02513 ,  H01L21/02521 ,  H01L21/0254 ,  H01L21/02603 ,  H01L21/02639 ,  H01L33/007 ,  H01L33/06 ,  H01L33/08 ,  H01L33/16 ,  H01L33/24 ,  H01L33/44 ,  H01L2933/0025

Abstract: A LED structure includes a support and a plurality of nanowires located on the support, where each nanowire includes a tip and a sidewall. A method of making the LED structure includes reducing or eliminating the conductivity of the tips of the nanowires compared to the conductivity of the sidewalls during or after creation of the nanowires.

公开(公告)号：US09997706B2

公开(公告)日：2018-06-12

申请号：US13913108

申请日：2013-06-07

Applicant: SAMSUNG RESEARCH AMERICA, INC.

Inventor： Justin W. Kamplain ,  Zhengguo Zhu

IPC: H01L49/00 ,  C30B29/40 ,  H01B1/12 ,  B82Y40/00 ,  H01L21/02 ,  B82Y30/00 ,  C09K11/02 ,  C09K11/56 ,  C09K11/74 ,  C09K11/88 ,  H01L29/06

CPC classification number: H01L49/006 ,  B82Y30/00 ,  B82Y40/00 ,  C09K11/02 ,  C09K11/565 ,  C09K11/7492 ,  C09K11/883 ,  C30B29/40 ,  H01L21/02439 ,  H01L21/02521 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02557 ,  H01L21/0256 ,  H01L21/02601 ,  H01L21/02628 ,  H01L21/02664 ,  H01L29/0665 ,  Y10S977/774 ,  Y10S977/896

Abstract: A method for preparing semiconductor nanocrystals is disclosed. The method comprises adding a precursor mixture comprising one or more cation precursors, one or more anion precursors, and one or more amines to a ligand mixture including one or more acids, one or more phenol compounds, and a solvent to form a reaction mixture, wherein the molar ratio of (the one or more phenol compounds plus the one or more acids plus the one or more amine compounds) to the one or more cations initially included in the reaction mixture is greater than or equal to about 6, and heating the reaction mixture at a temperature and for a period of time sufficient to produce semiconductor nanocrystals having a predetermined composition. Methods for forming a buffer layer and/or an overcoating layer thereover are also disclosed. Semiconductor nanocrystals and compositions including semiconductor nanocrystals of the invention are also disclosed. In certain embodiments, a semiconductor nanocrystal includes one or more Group IIIA and one or more Group VA elements.

公开(公告)号：US09722113B2

公开(公告)日：2017-08-01

申请号：US14807378

申请日：2015-07-23

Applicant: The Regents of the University of Michigan

Inventor： Vladimir A. Stoica ,  Lynn Endicott ,  Roy Clarke ,  Ctirad Uher

IPC: H01L31/032 ,  H01L31/18 ,  H01L33/00 ,  H01L33/12 ,  H01L31/0352 ,  H01L33/26 ,  H01L31/0725 ,  H01L21/66

CPC classification number: H01L31/0322 ,  H01L21/02439 ,  H01L21/02444 ,  H01L21/02483 ,  H01L21/02485 ,  H01L21/02502 ,  H01L21/02551 ,  H01L21/02568 ,  H01L21/02631 ,  H01L22/12 ,  H01L31/032 ,  H01L31/0326 ,  H01L31/035272 ,  H01L31/0392 ,  H01L31/072 ,  H01L31/0725 ,  H01L31/18 ,  H01L31/1864 ,  H01L33/005 ,  H01L33/12 ,  H01L33/26 ,  Y02E10/541

Abstract: A multilayer stack including a substrate, an active layer, and a tetradymite buffer layer positioned between the substrate and the active layer is disclosed. A method for fabricating a multilayer stack including a substrate, a tetradymite buffer layer and an active layer is also disclosed. Use of such stacks may be in photovoltaics, solar cells, light emitting diodes, and night vision arrays, among other applications.

公开(公告)号：US09711534B2

公开(公告)日：2017-07-18

申请号：US14353995

申请日：2011-10-28

Applicant: Di Liang ,  Raymond G Beausoleil

Inventor： Di Liang ,  Raymond G Beausoleil

IPC: G02B6/122 ,  H01L27/12 ,  H01L21/02 ,  H01L21/82

CPC classification number: H01L27/1203 ,  G02B6/122 ,  H01L21/02439 ,  H01L21/02444 ,  H01L21/02494 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/8213 ,  H01L27/12

Abstract: A device includes a substrate layer, a diamond layer, and a device layer. The device layer is patterned. The diamond layer is to conform to a pattern associated with the device layer.

公开(公告)号：US20170069716A1

公开(公告)日：2017-03-09

申请号：US14847260

申请日：2015-09-08

Applicant: M/A-COM Technology Solutions Holdings, Inc.

Inventor： John Claassen Roberts ,  Kevin J. Linthicum

IPC: H01L29/10 ,  H01L29/205 ,  H01L29/66 ,  H01L21/02 ,  H01L29/778 ,  H01L29/20 ,  H01L29/36

CPC classification number: H01L21/0254 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02439 ,  H01L21/02458 ,  H01L21/02502 ,  H01L21/0262 ,  H01L21/26506 ,  H01L21/266 ,  H01L29/0623 ,  H01L29/2003 ,  H01L29/32 ,  H01L29/41758 ,  H01L29/7783

Abstract: III-nitride materials are generally described herein, including material structures comprising III-nitride material regions and silicon-containing substrates. Certain embodiments are related to gallium nitride materials and material structures comprising gallium nitride material regions and silicon-containing substrates.

Abstract translation: 这里通常描述III族氮化物材料，包括包含III族氮化物材料区域和含硅衬底的材料结构。 某些实施例涉及氮化镓材料和包含氮化镓材料区域和含硅衬底的材料结构。

公开(公告)号：US20170040438A1

公开(公告)日：2017-02-09

申请号：US15295938

申请日：2016-10-17

Applicant: INTEL CORPORATION

Inventor： ANNALISA CAPPELLANI ,  VAN H. LE ,  GLENN A. GLASS ,  KELIN J. KUHN ,  STEPHEN M. CEA

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/306 ,  H01L21/762 ,  H01L29/06 ,  H01L21/02

CPC classification number: H01L29/66795 ,  H01L21/02233 ,  H01L21/02236 ,  H01L21/02238 ,  H01L21/02241 ,  H01L21/02255 ,  H01L21/02304 ,  H01L21/02439 ,  H01L21/0245 ,  H01L21/02455 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/306 ,  H01L21/76 ,  H01L21/7624 ,  H01L21/76283 ,  H01L29/0603 ,  H01L29/0642 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/1054 ,  H01L29/7378 ,  H01L29/785 ,  H01L33/12 ,  H05K1/18

Abstract: Techniques are disclosed for converting a strain-inducing semiconductor buffer layer into an electrical insulator at one or more locations of the buffer layer, thereby allowing an above device layer to have a number of benefits, which in some embodiments include those that arise from being grown on a strain-inducing buffer and having a buried electrical insulator layer. For instance, having a buried electrical insulator layer (initially used as a strain-inducing buffer during fabrication of the above active device layer) between the Fin and substrate of a non-planar integrated transistor circuit may simultaneously enable a low-doped Fin with high mobility, desirable device electrostatics and elimination or otherwise reduction of substrate junction leakage. Also, the presence of such an electrical insulator under the source and drain regions may further significantly reduce junction leakage. In some embodiments, substantially the entire buffer layer is converted to an electrical insulator.

Abstract translation: 公开了用于将应变诱导半导体缓冲层转化为缓冲层的一个或多个位置处的电绝缘体的技术，从而允许上述器件层具有许多益处，其在一些实施例中包括由于生长而产生的那些 在应变诱导缓冲器上并具有埋入的电绝缘体层。 例如，在非平面集成晶体管电路的Fin和衬底之间具有埋入的电绝缘体层（最初用作制造上述有源器件层期间的应变诱导缓冲器）可以同时使得具有高的低掺杂Fin 移动性，期望的器件静电，以及消除或以其他方式减少衬底结泄漏。 此外，源极和漏极区域下的这种电绝缘体的存在可以进一步显着减少结漏电。 在一些实施例中，基本上整个缓冲层被转换成电绝缘体。

公开(公告)号：US20160336171A1

公开(公告)日：2016-11-17

申请号：US15159976

申请日：2016-05-20

Applicant: The Government of the United States of America, as represented by the Secretary of the Navy

Inventor： Jennifer K. Hite ,  Francis J. Kub ,  Charles R. Eddy, JR. ,  Nelson Garces

IPC: H01L21/02

CPC classification number: H01L21/0254 ,  H01L21/0237 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02389 ,  H01L21/0242 ,  H01L21/02439 ,  H01L21/02458 ,  H01L21/02494 ,  H01L21/02502 ,  H01L21/0262 ,  H01L21/02639

Abstract: Disclosed herein is a method of: depositing a patterned mask layer on an N-polar GaN epitaxial layer of a sapphire, silicon, or silicon carbide substrate; depositing an AlN inversion layer on the open areas; removing any remaining mask; and depositing a III-N epitaxial layer to simultaneously produce N-polar material and III-polar material. Also disclosed herein is: depositing an AlN inversion layer on an N-polar bulk III-N substrate and depositing a III-N epitaxial layer to produce III-polar material. Also disclosed herein is: depositing an inversion layer on a III-polar bulk III-N substrate and depositing a III-N epitaxial layer to produce N-polar material. Also disclosed herein is a composition having: a bulk III-N substrate; an inversion layer on portions of the substrate; and a III-N epitaxial layer on the inversion layer. The III-N epitaxial layer is of the opposite polarity of the surface of the substrate.

Abstract translation: 本文公开了一种方法：在蓝宝石，硅或碳化硅衬底的N极GaN外延层上沉积图案化掩模层; 在开放区域上沉积AlN反转层; 去除任何剩余的面罩; 并沉积III-N外延层以同时产生N-极性材料和III-极性材料。 本文还公开的是：在N极本体III-N衬底上沉积AlN反转层并沉积III-N外延层以产生III极性材料。 本文还公开：在III极本体III-N衬底上沉积反型层并沉积III-N外延层以产生N-极性材料。 本文还公开了具有：本体III-N底物的组合物; 在基板的部分上的反转层; 和反型层上的III-N外延层。 III-N外延层具有与衬底表面相反的极性。