公开(公告)号：US07338849B2

公开(公告)日：2008-03-04

申请号：US11261820

申请日：2005-10-28

申请人： Dong-Chan Kim ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Dong-Hyun Kim

发明人： Dong-Chan Kim ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Dong-Hyun Kim

IPC分类号： H01L21/8238 ,  H01L29/788

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： Methods of fabricating a flash memory device and flash memory devices fabricated thereby are provided. One of the methods includes forming an isolation layer in a semiconductor substrate to define a plurality of parallel active regions in the semiconductor substrate. A plurality of first conductive layer patterns are formed on the active regions. The first conductive layer patterns are spaced apart from each other in a lengthwise direction of the active regions. An insulating layer is conformally formed on the semiconductor substrate and the first conductive layer patterns. A second conductive layer is formed on the insulating layer. The second conductive layer is patterned until the insulating layer is exposed to form a plurality of parallel second conductive layer patterns. The second conductive layer patterns cross the active regions and the isolation layer to overlap the first conductive layer patterns.

摘要翻译： 提供了制造闪速存储器件的方法和由此制造的闪存器件。 一种方法包括在半导体衬底中形成隔离层以在半导体衬底中限定多个平行的有源区。 在有源区上形成多个第一导电层图案。 第一导电层图案在活性区域的长度方向上彼此间隔开。 在半导体衬底和第一导电层图案上共形形成绝缘层。 在绝缘层上形成第二导电层。 图案化第二导电层直到绝缘层暴露以形成多个平行的第二导电层图案。 第二导电层图案与有源区和隔离层交叉，以与第一导电层图案重叠。

公开(公告)号：US20060094188A1

公开(公告)日：2006-05-04

申请号：US11261820

申请日：2005-10-28

申请人： Dong-Chan Kim ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Dong-Hyun Kim

发明人： Dong-Chan Kim ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Dong-Hyun Kim

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： Methods of fabricating a flash memory device and flash memory devices fabricated thereby are provided. One of the methods includes forming an isolation layer in a semiconductor substrate to define a plurality of parallel active regions in the semiconductor substrate. A plurality of first conductive layer patterns are formed on the active regions. The first conductive layer patterns are spaced apart from each other in a lengthwise direction of the active regions. An insulating layer is conformally formed on the semiconductor substrate and the first conductive layer patterns. A second conductive layer is formed on the insulating layer. The second conductive layer is patterned until the insulating layer is exposed to form a plurality of parallel second conductive layer patterns. The second conductive layer patterns cross the active regions and the isolation layer to overlap the first conductive layer patterns.

摘要翻译： 提供了制造闪速存储器件的方法和由此制造的闪存器件。 一种方法包括在半导体衬底中形成隔离层以在半导体衬底中限定多个平行的有源区。 在有源区上形成多个第一导电层图案。 第一导电层图案在活性区域的长度方向上彼此间隔开。 在半导体衬底和第一导电层图案上共形形成绝缘层。 在绝缘层上形成第二导电层。 图案化第二导电层直到绝缘层暴露以形成多个平行的第二导电层图案。 第二导电层图案与有源区和隔离层交叉，以与第一导电层图案重叠。

公开(公告)号：US07479445B2

公开(公告)日：2009-01-20

申请号：US11247937

申请日：2005-10-11

申请人： Dong-Chan Kim ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Sung-Hoon Chung

发明人： Dong-Chan Kim ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Sung-Hoon Chung

IPC分类号： H01L21/28 ,  H01L21/335

CPC分类号： H01L29/1037 ,  H01L21/823437 ,  H01L21/823456 ,  H01L29/76

摘要： Methods of forming field effect transistors include forming a first electrically insulating layer comprising mostly carbon on a surface of a semiconductor substrate and patterning the first electrically insulating layer to define an opening therein. A trench is formed in the substrate by etching the surface of the substrate using the patterned first electrically insulating layer as an etching mask. The trench is filled with a gate electrode. The first electrically insulating layer is patterned in an ambient containing oxygen. This oxygen-containing ambient supports further oxidation of trench-based isolation regions within the substrate when they are exposed by openings within the first electrically insulating layer.

摘要翻译： 形成场效应晶体管的方法包括在半导体衬底的表面上形成主要包含碳的第一电绝缘层，并且图案化第一电绝缘层以在其中限定开口。 通过使用图案化的第一电绝缘层作为蚀刻掩模蚀刻衬底的表面，在衬底中形成沟槽。 沟槽填充有栅电极。 第一电绝缘层在含有氧的环境中被图案化。 当这种含氧环境通过第一电绝缘层内的开口露出时，支撑衬底内基于沟槽的隔离区的进一步氧化。

公开(公告)号：US07384843B2

公开(公告)日：2008-06-10

申请号：US11260377

申请日：2005-10-28

申请人： Dong-Chan Kim ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Seung-Pil Chung

发明人： Dong-Chan Kim ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Seung-Pil Chung

IPC分类号： H01L21/336

CPC分类号： H01L27/11524 ,  H01L21/28273 ,  H01L27/11521

摘要： A method of manufacturing a semiconductor memory device comprises forming floating gates on active regions of a semiconductor substrate and forming a capping layer on the floating gates. An isolation layer located in the semiconductor substrate between the floating gates is anisotropically etched using the capping layer as an etch mask to form recessed regions. The recessed regions are formed to have a width smaller than a distance between the floating gates, and bottom surfaces positioned below bottom surfaces of the floating gates. Control gate electrodes are formed across the active regions over the floating gates and the control gate electrodes have control gate extensions formed within the recessed regions between the floating gates.

摘要翻译： 制造半导体存储器件的方法包括在半导体衬底的有源区上形成浮置栅极，并在浮置栅极上形成封盖层。 使用覆盖层作为蚀刻掩模对位于浮置栅极之间的半导体衬底中的隔离层进行各向异性蚀刻，以形成凹陷区域。 凹陷区域形成为具有小于浮动栅极之间的距离的宽度，以及位于浮动栅极的底表面下方的底表面的宽度。 控制栅电极形成在浮动栅极之上的有源区域两侧，并且控制栅电极具有形成在浮置栅极之间的凹陷区域内的控制栅延伸。

公开(公告)号：US07125766B2

公开(公告)日：2006-10-24

申请号：US11062546

申请日：2005-02-23

申请人： Dong-Chan Kim ,  Chang-Jin Kang ,  Byeong-Yun Nam ,  Kyeong-Koo Chi

发明人： Dong-Chan Kim ,  Chang-Jin Kang ,  Byeong-Yun Nam ,  Kyeong-Koo Chi

IPC分类号： H01L21/8242

CPC分类号： H01L28/91 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/10855

摘要： A method of forming a capacitor for a semiconductor device is disclosed. According to the method, a silicon germanium layer and an oxide layer are used as mold layers for forming a storage electrode. The oxide layer and the silicon germanium layer are anisotropically etched to form an opening and then the silicon germanium layer is further isotropically etched to form a recessed portion of the opening, such that the recessed portion of the opening formed in the silicon germanium layer is wider than at least some portion of the opening through the oxide layer. Thus, the mold layers are used to form a storage electrode having a lower portion which is wider than an upper portion thereof.

摘要翻译： 公开了一种形成用于半导体器件的电容器的方法。 根据该方法，使用硅锗层和氧化物层作为用于形成存储电极的模具层。 各向异性蚀刻氧化物层和硅锗层以形成开口，然后进一步各向同性地蚀刻硅锗层以形成开口的凹部，使得形成在硅锗层中的开口的凹部变宽 比通过氧化物层的开口的至少一部分。 因此，模具层用于形成具有比其上部宽的下部的存储电极。

公开(公告)号：US20060128099A1

公开(公告)日：2006-06-15

申请号：US11260377

申请日：2005-10-28

申请人： Dong-Chan Kim ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Seung-Pil Chung

发明人： Dong-Chan Kim ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Seung-Pil Chung

IPC分类号： H01L21/336

CPC分类号： H01L27/11524 ,  H01L21/28273 ,  H01L27/11521

摘要： A method of manufacturing a semiconductor memory device comprises forming floating gates on active regions of a semiconductor substrate and forming a capping layer on the floating gates. An isolation layer located in the semiconductor substrate between the floating gates is anisotropically etched using the capping layer as an etch mask to form recessed regions. The recessed regions are formed to have a width smaller than a distance between the floating gates, and bottom surfaces positioned below bottom surfaces of the floating gates. Control gate electrodes are formed across the active regions over the floating gates and the control gate electrodes have control gate extensions formed within the recessed regions between the floating gates.

摘要翻译： 制造半导体存储器件的方法包括在半导体衬底的有源区上形成浮置栅极，并在浮置栅极上形成封盖层。 使用覆盖层作为蚀刻掩模对位于浮置栅极之间的半导体衬底中的隔离层进行各向异性蚀刻，以形成凹陷区域。 凹陷区域形成为具有小于浮动栅极之间的距离的宽度，以及位于浮动栅极的底表面下方的底表面的宽度。 控制栅电极形成在浮动栅极之上的有源区域两侧，并且控制栅电极具有形成在浮置栅极之间的凹陷区域内的控制栅延伸。

公开(公告)号：US20060079076A1

公开(公告)日：2006-04-13

申请号：US11247937

申请日：2005-10-11

申请人： Dong-Chan Kim ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Sung-Hoon Chung

发明人： Dong-Chan Kim ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Sung-Hoon Chung

IPC分类号： H01L21/3205 ,  H01L21/336 ,  H01L21/8234

CPC分类号： H01L29/1037 ,  H01L21/823437 ,  H01L21/823456 ,  H01L29/76

摘要： Methods of forming field effect transistors include forming a first electrically insulating layer comprising mostly carbon on a surface of a semiconductor substrate and patterning the first electrically insulating layer to define an opening therein. A trench is formed in the substrate by etching the surface of the substrate using the patterned first electrically insulating layer as an etching mask. The trench is filled with a gate electrode. The first electrically insulating layer is patterned in an ambient containing oxygen. This oxygen-containing ambient supports further oxidation of trench-based isolation regions within the substrate when they are exposed by openings within the first electrically insulating layer.

公开(公告)号：US20050245026A1

公开(公告)日：2005-11-03

申请号：US11062546

申请日：2005-02-23

申请人： Dong-Chan Kim ,  Chang-Jin Kang ,  Byeong-Yun Nam ,  Kyeong-Koo Chi

发明人： Dong-Chan Kim ,  Chang-Jin Kang ,  Byeong-Yun Nam ,  Kyeong-Koo Chi

IPC分类号： H01L27/108 ,  H01L21/02 ,  H01L21/8242

CPC分类号： H01L28/91 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/10855

摘要： A method of forming a capacitor for a semiconductor device is disclosed. According to the method, a silicon germanium layer and an oxide layer are used as mold layers for forming a storage electrode. The oxide layer and the silicon germanium layer are anisotropically etched to form an opening and then the silicon germanium layer is further isotropically etched to form a recessed portion of the opening, such that the recessed portion of the opening formed in the silicon germanium layer is wider than at least some portion of the opening through the oxide layer. Thus, the mold layers are used to form a storage electrode having a lower portion which is wider than an upper portion thereof.

摘要翻译： 公开了一种形成用于半导体器件的电容器的方法。 根据该方法，使用硅锗层和氧化物层作为用于形成存储电极的模具层。 各向异性蚀刻氧化物层和硅锗层以形成开口，然后进一步各向同性地蚀刻硅锗层以形成开口的凹部，使得形成在硅锗层中的开口的凹部变宽 比通过氧化物层的开口的至少一部分。 因此，模具层用于形成具有比其上部宽的下部的存储电极。

公开(公告)号：US20080087931A1

公开(公告)日：2008-04-17

申请号：US11869400

申请日：2007-10-09

申请人： Sung-Il Cho ,  Seung-Young Son ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Ji-Chul Shin

发明人： Sung-Il Cho ,  Seung-Young Son ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Ji-Chul Shin

IPC分类号： H01L27/108 ,  H01L21/3205 ,  H01L21/8242

CPC分类号： H01L28/91 ,  H01L21/3142 ,  H01L21/31616 ,  H01L21/31645 ,  H01L21/32136 ,  H01L27/10855

摘要： Methods are provided for fabricating semiconductor devices having capacitors, which prevent lower electrodes of the capacitors from breaking or collapsing and which provide increased capacitance of the capacitors. For instance, a method includes forming a first insulating layer on a semiconductor substrate, forming a first hole in the first insulating layer, forming a contact plug in the first hole, forming a second insulating layer having a landing pad, wherein the landing pad contacts an upper surface of the contact plug, forming an etch stop layer on the landing pad and the second insulating layer, forming a third insulating layer on the etch stop layer, forming a third hole through the third insulating layer and etch stop layer to expose the landing pad, selectively etching the exposed landing pad, forming a lower electrode on the selectively etched landing pad, and then forming a capacitor by forming a dielectric layer and an upper electrode on the lower electrode.

摘要翻译： 提供了用于制造具有电容器的半导体器件的方法，其阻止电容器的下部电极断开或塌缩并且提供电容器的增加的电容。 例如，一种方法包括在半导体衬底上形成第一绝缘层，在第一绝缘层中形成第一孔，在第一孔中形成接触塞，形成具有着陆垫的第二绝缘层，其中， 所述接触插塞的上表面在所述着陆焊盘和所述第二绝缘层上形成蚀刻停止层，在所述蚀刻停止层上形成第三绝缘层，形成通过所述第三绝缘层的第三孔和蚀刻停止层， 选择性地蚀刻暴露的着陆焊盘，在选择性蚀刻的着陆焊盘上形成下电极，然后通过在下电极上形成电介质层和上电极来形成电容器。

公开(公告)号：US20080081432A1

公开(公告)日：2008-04-03

申请号：US11624905

申请日：2007-01-19

申请人： Yong-Jin KIM ,  Kyeong-Koo Chi ,  Chang-Jin Kang ,  Hyoung-Sub Kim ,  Mybong-Cheol Kim ,  Tae-Rin Chung ,  Sung-Hoon Chung ,  Ji-Young Kim

发明人： Yong-Jin KIM ,  Kyeong-Koo Chi ,  Chang-Jin Kang ,  Hyoung-Sub Kim ,  Mybong-Cheol Kim ,  Tae-Rin Chung ,  Sung-Hoon Chung ,  Ji-Young Kim

IPC分类号： H01L21/76

CPC分类号： H01L29/66621 ,  H01L21/823437 ,  H01L27/10876 ,  H01L29/7834

摘要： A semiconductor device includes a plurality of gate trenches, each of which has first inner walls, which face each other in a first direction which is perpendicular to a second direction in which active regions extend, and second inner walls, which face each other in the second direction in which the active regions extends. An isolation layer contacts a gate insulating layer throughout the entire length of the first inner wails of the gate trenches including from entrance portions of the gate trenches to bottom portions of the gate trenches, and a plurality of channel regions are disposed adjacent to the gate insulating layers in the semiconductor substrate along the second inner walls and the bottom portions of the gate trenches.

摘要翻译： 半导体器件包括多个栅极沟槽，每个栅极沟槽具有第一内壁，该第一内壁沿与第一方向相对的第一方向，该第一方向垂直于有源区域延伸的第二方向;以及第二内壁， 活动区域延伸的第二方向。 隔离层在包括从栅极沟槽的入口部分到栅极沟槽的底部的栅极沟槽的整个长度的整个长度上接触栅极绝缘层，并且多个沟道区域邻近栅极绝缘体 沿着第二内壁和栅极沟槽的底部的半导体衬底中的层。