Metal wiring layer and method of fabricating the same
    1.
    发明申请
    Metal wiring layer and method of fabricating the same 有权
    金属布线层及其制造方法

    公开(公告)号:US20090115066A1

    公开(公告)日:2009-05-07

    申请号:US12290594

    申请日:2008-10-31

    IPC分类号: H01L23/535 H01L21/768

    摘要: A metal wiring layer and a method of fabricating the metal wiring layer are provided. The method includes forming a dielectric layer on a substrate, forming a plurality of dielectric layer patterns and holes therein on the substrate by etching part of the dielectric layer, with a cross sectional area of the holes in the dielectric layer patterns decreasing with increasing distance away from the substrate and the holes exposing the substrate, forming a trench by etching a portion of the substrate exposed through the holes in the dielectric layer patterns, and forming a metal layer which fills the trench and the holes in the dielectric layer patterns. Thus, it is possible to prevent the occurrence of an edge build-up phenomenon by forming a metal layer in a plurality of holes in the dielectric layer patterns having a cross sectional area decreasing with increasing distance away from the substrate. Therefore, it is possible to prevent the transmittance of a liquid crystal layer from decreasing due to a failure to properly fill liquid crystal molecules in the liquid crystal layer, and thus to increase the quality of display.

    摘要翻译: 提供金属布线层和制造金属布线层的方法。 该方法包括在衬底上形成电介质层,通过蚀刻介电层的一部分,在衬底上形成多个介电层图案和孔,电介质层图案中的孔的横截面积随距离的增加而减小 从衬底和暴露衬底的孔,通过蚀刻通过介电层图案中的孔暴露的衬底的一部分形成沟槽,以及形成填充沟槽和介电层图案中的空穴的金属层。 因此,可以通过在电介质层图案中的多个孔中形成金属层来防止边缘积聚现象的发生,该电介质层图案的横截面积随离开距衬底的距离的增加而减小。 因此,可以防止液晶层的透射率由于不能适当地填充液晶层中的液晶分子而降低,从而提高显示质量。

    Metal wiring layer and method of fabricating the same
    2.
    发明授权
    Metal wiring layer and method of fabricating the same 有权
    金属布线层及其制造方法

    公开(公告)号:US08211797B2

    公开(公告)日:2012-07-03

    申请号:US12290594

    申请日:2008-10-31

    IPC分类号: H01L21/44

    摘要: A metal wiring layer and a method of fabricating the metal wiring layer are provided. The method includes forming a dielectric layer on a substrate, forming a plurality of dielectric layer patterns and holes therein on the substrate by etching part of the dielectric layer, with a cross sectional area of the holes in the dielectric layer patterns decreasing with increasing distance away from the substrate and the holes exposing the substrate, forming a trench by etching a portion of the substrate exposed through the holes in the dielectric layer patterns, and forming a metal layer which fills the trench and the holes in the dielectric layer patterns. Thus, it is possible to prevent the occurrence of an edge build-up phenomenon by forming a metal layer in a plurality of holes in the dielectric layer patterns having a cross sectional area decreasing with increasing distance away from the substrate. Therefore, it is possible to prevent the transmittance of a liquid crystal layer from decreasing due to a failure to properly fill liquid crystal molecules in the liquid crystal layer, and thus to increase the quality of display.

    摘要翻译: 提供金属布线层和制造金属布线层的方法。 该方法包括在衬底上形成电介质层,通过蚀刻介电层的一部分,在衬底上形成多个介电层图案和孔,电介质层图案中的孔的横截面积随距离的增加而减小 从衬底和暴露衬底的孔,通过蚀刻通过介电层图案中的孔暴露的衬底的一部分形成沟槽,以及形成填充沟槽和介电层图案中的空穴的金属层。 因此,可以通过在电介质层图案中的多个孔中形成金属层来防止边缘积聚现象的发生,该电介质层图案的横截面积随离开距衬底的距离的增加而减小。 因此,可以防止液晶层的透射率由于不能适当地填充液晶层中的液晶分子而降低,从而提高显示质量。

    THIN FILM TRANSISTOR ARRAY SUBSTRATE AND METHOD OF FABRICATING THE SAME
    5.
    发明申请
    THIN FILM TRANSISTOR ARRAY SUBSTRATE AND METHOD OF FABRICATING THE SAME 有权
    薄膜晶体管阵列基板及其制造方法

    公开(公告)号:US20100163862A1

    公开(公告)日:2010-07-01

    申请号:US12484116

    申请日:2009-06-12

    摘要: A method of fabricating a thin film transistor array substrate is presented. The method entails forming a gate interconnection line on an insulating substrate, forming a gate insulating layer on the gate interconnection line, forming a semiconductor layer and a data interconnection line on the semiconductor layer, sequentially forming multiple passivation layers, etching the passivation layers down to a drain electrode that is an extension of the data interconnection line. The portion of the drain electrode that is exposed at this stage is a part of the drain electrode-pixel electrode contact portion. A pixel electrode is formed connected to the drain electrode. Two of the passivation layers have the same composition but are processed at different temperatures. A thin film transistor prepared in the above manner is also presented.

    摘要翻译: 提出了制造薄膜晶体管阵列基板的方法。 该方法需要在绝缘基板上形成栅极互连线,在栅极互连线上形成栅极绝缘层,在半导体层上形成半导体层和数据互连线,依次形成多个钝化层,将钝化层蚀刻到 作为数据互连线的延伸线的漏电极。 在该阶段暴露的漏电极的部分是漏极电极 - 像素电极接触部分的一部分。 形成连接到漏电极的像素电极。 两个钝化层具有相同的组成,但是在不同的温度下进行处理。 还提出了以上述方式制备的薄膜晶体管。

    Method of fabricating a thin film transistor array substrate
    6.
    发明授权
    Method of fabricating a thin film transistor array substrate 有权
    制造薄膜晶体管阵列基板的方法

    公开(公告)号:US08586990B2

    公开(公告)日:2013-11-19

    申请号:US13210282

    申请日:2011-08-15

    IPC分类号: H01L27/14

    摘要: A method of fabricating a thin film transistor array substrate is presented. The method entails forming a gate interconnection line on an insulating substrate, forming a gate insulating layer on the gate interconnection line, forming a semiconductor layer and a data interconnection line on the semiconductor layer, sequentially forming multiple passivation layers, etching the passivation layers down to a drain electrode that is an extension of the data interconnection line. The portion of the drain electrode that is exposed at this stage is a part of the drain electrode-pixel electrode contact portion. A pixel electrode is formed connected to the drain electrode. Two of the passivation layers have the same composition but are processed at different temperatures. A thin film transistor prepared in the above manner is also presented.

    摘要翻译: 提出了制造薄膜晶体管阵列基板的方法。 该方法需要在绝缘基板上形成栅极互连线,在栅极互连线上形成栅极绝缘层,在半导体层上形成半导体层和数据互连线,依次形成多个钝化层,将钝化层蚀刻到 作为数据互连线的延伸线的漏电极。 在该阶段暴露的漏电极的部分是漏极电极 - 像素电极接触部分的一部分。 形成连接到漏电极的像素电极。 两个钝化层具有相同的组成,但是在不同的温度下进行处理。 还提出了以上述方式制备的薄膜晶体管。

    Method of fabricating a thin film transistor array substrate
    7.
    发明授权
    Method of fabricating a thin film transistor array substrate 有权
    制造薄膜晶体管阵列基板的方法

    公开(公告)号:US08017459B2

    公开(公告)日:2011-09-13

    申请号:US12484116

    申请日:2009-06-12

    IPC分类号: H01L21/00

    摘要: A method of fabricating a thin film transistor array substrate is presented. The method entails forming a gate interconnection line on an insulating substrate, forming a gate insulating layer on the gate interconnection line, forming a semiconductor layer and a data interconnection line on the semiconductor layer, sequentially forming multiple passivation layers, etching the passivation layers down to a drain electrode that is an extension of the data interconnection line. The portion of the drain electrode that is exposed at this stage is a part of the drain electrode-pixel electrode contact portion. A pixel electrode is formed connected to the drain electrode. Two of the passivation layers have the same composition but are processed at different temperatures. A thin film transistor prepared in the above manner is also presented.

    摘要翻译: 提出了制造薄膜晶体管阵列基板的方法。 该方法需要在绝缘基板上形成栅极互连线,在栅极互连线上形成栅极绝缘层,在半导体层上形成半导体层和数据互连线,依次形成多个钝化层,将钝化层蚀刻到 作为数据互连线的延伸线的漏电极。 在该阶段暴露的漏电极的部分是漏极电极 - 像素电极接触部分的一部分。 形成连接到漏电极的像素电极。 两个钝化层具有相同的组成,但是在不同的温度下进行处理。 还提出了以上述方式制备的薄膜晶体管。

    THIN-FILM TRANSISTOR SUBSTRATE AND METHOD OF FABRICATING THE SAME
    10.
    发明申请
    THIN-FILM TRANSISTOR SUBSTRATE AND METHOD OF FABRICATING THE SAME 审中-公开
    薄膜晶体管基板及其制造方法

    公开(公告)号:US20100032760A1

    公开(公告)日:2010-02-11

    申请号:US12508972

    申请日:2009-07-24

    IPC分类号: H01L29/786 H01L21/20

    摘要: The present invention provides a thin-film transistor (TFT) substrate, which can be fabricated simply and at reduced cost, and a method of fabricating the TFT substrate. The TFT substrate includes: an insulating substrate; gate wiring that extends on the insulating substrate in a first direction; data wiring that extends on the gate wiring in a second direction, and includes a lower layer and an upper layer; and a semiconductor pattern that is disposed under the data wiring and has substantially the same shape as the data wiring except for a channel region, wherein root-mean-square roughness of a top surface of the data wiring is 3 nm or less.

    摘要翻译: 本发明提供了可以简单且成本低廉地制造的薄膜晶体管(TFT)基板,以及制造TFT基板的方法。 TFT基板包括:绝缘基板; 在第一方向上在绝缘基板上延伸的栅极布线; 数据布线,其在第二方向上在栅极布线上延伸,并且包括下层和上层; 以及配置在数据配线下方的半导体图形,并且具有与除了沟道区域以外的数据布线基本相同的形状,其中数据布线的顶面的均方根粗糙度为3nm以下。