公开(公告)号：US20140140124A1

公开(公告)日：2014-05-22

申请号：US14078530

申请日：2013-11-13

申请人： Dong-Seok KANG ,  CHANKYUNG KIM ,  YUNSANG LEE ,  Soo-Ho CHA

发明人： Dong-Seok KANG ,  CHANKYUNG KIM ,  YUNSANG LEE ,  Soo-Ho CHA

IPC分类号： G11C13/00

CPC分类号： G11C13/004 ,  G11C5/025 ,  G11C11/1673 ,  G11C2213/77 ,  G11C2213/79

摘要： A method of controlling a read operation of a resistive memory device is provided which includes activating at least one of a plurality of word lines in response to a first command; after receiving a second command, sensing data of a memory cell, corresponding to a selected page, from among all memory cells connected with the activated word line through a corresponding bit line sense amplifier; and outputting the sensed data as read data according to a sensing output control signal.

摘要翻译： 提供了一种控制电阻式存储器件的读取操作的方法，其包括响应于第一命令激活多个字线中的至少一个; 在接收到第二命令之后，通过相应的位线读出放大器从与所激活的字线连接的所有存储单元中感测与选定页相对应的存储单元的数据; 并且根据感测输出控制信号将所感测的数据输出为读取数据。

公开(公告)号：US20140146621A1

公开(公告)日：2014-05-29

申请号：US14082210

申请日：2013-11-18

申请人： CHANKYUNG KIM ,  SANGBO LEE ,  SEONGHYUN JEON

发明人： CHANKYUNG KIM ,  SANGBO LEE ,  SEONGHYUN JEON

IPC分类号： G11C7/00

CPC分类号： G11C7/1045 ,  G11C7/109 ,  G11C7/222 ,  G11C8/12 ,  G11C11/1653 ,  G11C11/1673 ,  G11C11/1675

摘要： A nonvolatile memory includes multiple banks, control logic and multiple read and write (RW) circuits. Each bank includes multiple memory cells. The control logic includes multiple storage units corresponding to the banks, respectively, and configured to output write enable signals and read enable signals to respective banks based on mode information stored in respective storage units. The RW circuits are connected to the banks, respectively, and are configured to independently enable or disable write and read operations of the respective banks in response to the write enable signals and the read enable signals of the respective banks. In an initial state after the mode information is stored in the respective storage units, the control logic activates the write enable signals and the read enable signals of the respective banks regardless of the mode information stored in the respective storage units.

摘要翻译： 非易失性存储器包括多个存储体，控制逻辑和多个读写（RW）电路。 每个存储体包括多个存储单元。 控制逻辑分别包括对应于存储体的多个存储单元，并且被配置为基于存储在各个存储单元中的模式信息，将写使能信号和使能信号读取到各个存储体。 RW电路分别连接到存储体，并且被配置为响应于写入使能信号和各个存储体的读取使能信号独立地使能或禁止各个存储体的写入和读取操作。 在模式信息被存储在各个存储单元中之后的初始状态下，无论存储在各个存储单元中的模式信息如何，控制逻辑激活各个存储体的写使能信号和读使能信号。

公开(公告)号：US20180108383A1

公开(公告)日：2018-04-19

申请号：US15820473

申请日：2017-11-22

申请人： CHANKYUNG KIM ,  UKSONG KANG ,  Nam Sung KIM

发明人： CHANKYUNG KIM ,  UKSONG KANG ,  Nam Sung KIM

IPC分类号： G11C5/02 ,  G11C5/06 ,  G06F12/06 ,  G11C11/406

CPC分类号： G11C5/02 ,  G06F12/0638 ,  G06F13/1636 ,  G06F2212/205 ,  G11C5/025 ,  G11C5/06 ,  G11C8/12 ,  G11C11/40611 ,  G11C14/0009

摘要： Disclosed is a memory package. The memory package includes a nonvolatile memory chip, a volatile memory chip of which an access speed is faster than an access speed of the nonvolatile memory chip, and a logic chip for performing a refresh operation about the volatile memory chip in response to a refresh command from an external device, and migrating at least a portion of data stored in the nonvolatile memory chip to the volatile memory chip when the refresh operation is performed.