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    Method for fabricating capacitor of semiconductor device
    2.
    发明授权
    Method for fabricating capacitor of semiconductor device 失效
    制造半导体器件电容器的方法

    公开(公告)号：US07666738B2

    公开(公告)日：2010-02-23

    申请号：US11952767

    申请日：2007-12-07

    申请人： Dong-Woo Shin ,  Hyung-Bok Choi ,  Jong-Min Lee ,  Jin-Woong Kim

    发明人： Dong-Woo Shin ,  Hyung-Bok Choi ,  Jong-Min Lee ,  Jin-Woong Kim

    IPC分类号： H01L21/8242

    CPC分类号： H01L28/84 ,  H01L21/32155 ,  H01L28/91

    摘要： The present invention relates to a method for fabricating a capacitor of a semiconductor device. The method includes the steps of: forming a first amorphous silicon layer doped with an impurity in a predetermined first doping concentration suppressing dopants from locally agglomerating; forming an impurity undoped second amorphous silicon layer on the first amorphous silicon layer in an in-situ condition; forming a storage node by patterning the first amorphous silicon layer and the second amorphous silicon layer; forming silicon grains on a surface of the storage node; and doping the impurity to the storage node and the silicon grains until reaching a second predetermined concentration for providing conductivity required by the storage node.

    摘要翻译： 本发明涉及半导体器件的电容器的制造方法。 该方法包括以下步骤：在预定的第一掺杂浓度抑制掺杂剂中形成掺杂有杂质的第一非晶硅层局部凝聚; 在原位条件下在第一非晶硅层上形成杂质未掺杂的第二非晶硅层; 通过图案化所述第一非晶硅层和所述第二非晶硅层来形成存储节点; 在所述存储节点的表面上形成硅晶粒; 以及将杂质掺杂到存储节点和硅晶粒直到达到第二预定浓度以提供存储节点所需的导电性。

    Capacitor and method for fabricating the same
    3.
    发明授权
    Capacitor and method for fabricating the same 失效
    电容器及其制造方法

    公开(公告)号：US07595526B2

    公开(公告)日：2009-09-29

    申请号：US11201306

    申请日：2005-08-11

    申请人： Dong-Woo Shin ,  Hyung-Bok Choi

    发明人： Dong-Woo Shin ,  Hyung-Bok Choi

    IPC分类号： H01L29/94

    CPC分类号： H01L28/84 ,  H01L27/10817 ,  H01L27/10852 ,  H01L28/90

    摘要： A method for manufacturing a capacitor in a semiconductor device for securing capacitance without a merging phenomenon during a MPS grain growth process. The manufacturing step begins with a preparation of a substrate. The interlayer dielectric (ILD) layer is formed on the substrate and is etched to form conductive plug. Then, an etch barrier layer and a sacrifice insulating layer are formed on entire surface subsequently. A cylinder typed first electrode is formed over the conductive plug using the sacrifice insulating layer. Thereafter, first meta-stable poly silicon (MPS) grains are formed on inner wall of the first electrode except a bottom region thereof. However, second MPS grains with small sizes can be formed in the bottom region for increasing a storage area of the first electrode. Finally, a dielectric layer and a second electrode are formed on the first electrode subsequently.

    摘要翻译： 一种用于在MPS晶粒生长过程中用于在没有合并现象的情况下确保电容的半导体器件中的电容器的制造方法。 制造步骤从制备基材开始。 层间电介质层（ILD）层形成在衬底上并被蚀刻以形成导电插塞。 然后，随后在整个表面上形成蚀刻阻挡层和牺牲绝缘层。 使用牺牲绝缘层在导电插塞上形成圆筒型第一电极。 此后，除了其底部区域之外，在第一电极的内壁上形成第一元稳定多晶硅（MPS）晶粒。 然而，可以在底部区域中形成具有小尺寸的第二MPS晶粒，以增加第一电极的存储面积。 最后，随后在第一电极上形成电介质层和第二电极。

    Method for fabricating capacitor of semiconductor device
    4.
    发明授权
    Method for fabricating capacitor of semiconductor device 有权
    制造半导体器件电容器的方法

    公开(公告)号：US07407854B2

    公开(公告)日：2008-08-05

    申请号：US10749775

    申请日：2003-12-30

    申请人： Dong-Woo Shin ,  Hyung-Bok Choi ,  Jong-Min Lee ,  Jin-Woong Kim

    发明人： Dong-Woo Shin ,  Hyung-Bok Choi ,  Jong-Min Lee ,  Jin-Woong Kim

    IPC分类号： H01L21/8242

    CPC分类号： H01L28/84 ,  H01L21/32155 ,  H01L28/91

    摘要： The present invention relates to a method for fabricating a capacitor of a semiconductor device. The method includes the steps of: forming a first amorphous silicon layer doped with an impurity in a predetermined first doping concentration suppressing dopants from locally agglomerating; forming an impurity undoped second amorphous silicon layer on the first amorphous silicon layer in an in-situ condition; forming a storage node by patterning the first amorphous silicon layer and the second amorphous silicon layer; forming silicon grains on a surface of the storage node; and doping the impurity to the storage node and the silicon grains until reaching a second predetermined concentration for providing conductivity required by the storage node.

    摘要翻译： 本发明涉及半导体器件的电容器的制造方法。 该方法包括以下步骤：在预定的第一掺杂浓度抑制掺杂剂中形成掺杂有杂质的第一非晶硅层局部凝聚; 在原位条件下在第一非晶硅层上形成杂质未掺杂的第二非晶硅层; 通过图案化所述第一非晶硅层和所述第二非晶硅层来形成存储节点; 在所述存储节点的表面上形成硅晶粒; 以及将杂质掺杂到存储节点和硅晶粒直到达到第二预定浓度以提供存储节点所需的导电性。

    Capacitor and method for fabricating the same
    6.
    发明申请
    Capacitor and method for fabricating the same 失效
    电容器及其制造方法

    公开(公告)号：US20050269618A1

    公开(公告)日：2005-12-08

    申请号：US11201306

    申请日：2005-08-11

    申请人： Dong-Woo Shin ,  Hyung-Bok Choi

    发明人： Dong-Woo Shin ,  Hyung-Bok Choi

    IPC分类号： H01L21/8242 ,  H01L21/02 ,  H01L27/108

    CPC分类号： H01L28/84 ,  H01L27/10817 ,  H01L27/10852 ,  H01L28/90

    摘要： A method for manufacturing a capacitor in a semiconductor device for securing capacitance without a merging phenomenon during a MPS grain growth process. The manufacturing step begins with a preparation of a substrate. The interlayer dielectric (ILD) layer is formed on the substrate and is etched to form conductive plug. Then, an etch barrier layer and a sacrifice insulating layer are formed on entire surface subsequently. A cylinder typed first electrode is formed over the conductive plug using the sacrifice insulating layer. Thereafter, first meta-stable poly silicon (MPS) grains are formed on inner wall of the first electrode except a bottom region thereof. However, second MPS grains with small sizes can be formed in the bottom region for increasing a storage area of the first electrode. Finally, a dielectric layer and a second electrode are formed on the first electrode subsequently.

    摘要翻译： 一种用于在MPS晶粒生长过程中用于在没有合并现象的情况下确保电容的半导体器件中的电容器的制造方法。 制造步骤从制备基材开始。 层间电介质层（ILD）层形成在衬底上并被蚀刻以形成导电插塞。 然后，随后在整个表面上形成蚀刻阻挡层和牺牲绝缘层。 使用牺牲绝缘层在导电插塞上形成圆筒型第一电极。 此后，除了其底部区域之外，在第一电极的内壁上形成第一元稳定多晶硅（MPS）晶粒。 然而，可以在底部区域中形成具有小尺寸的第二MPS晶粒，以增加第一电极的存储面积。 最后，随后在第一电极上形成电介质层和第二电极。

    Capacitor and method for fabricating the same
    7.
    发明授权
    Capacitor and method for fabricating the same 失效

    公开(公告)号：US06946356B2

    公开(公告)日：2005-09-20

    申请号：US10316898

    申请日：2002-12-12

    申请人： Dong-Woo Shin ,  Hyung-Bok Choi

    发明人： Dong-Woo Shin ,  Hyung-Bok Choi

    IPC分类号： H01L21/8242 ,  H01L21/02 ,  H01L27/108 ,  H01L21/20

    CPC分类号： H01L28/84 ,  H01L27/10817 ,  H01L27/10852 ,  H01L28/90

    摘要： A method for manufacturing a capacitor in a semiconductor device for securing capacitance without a merging phenomenon during a MPS grain growth process. The manufacturing step begins with a preparation of a substrate. The interlayer dielectric (ILD) layer is formed on the substrate and is etched to form conductive plug. Then, an etch barrier layer and a sacrifice insulating layer are formed on entire surface subsequently. A cylinder typed first electrode is formed over the conductive plug using the sacrifice insulating layer. Thereafter, first meta-stable poly silicon (MPS) grains are formed on inner wall of the first electrode except a bottom region thereof. However, second MPS grains with small sizes can be formed in the bottom region for increasing a storage area of the first electrode. Finally, a dielectric layer and a second electrode are formed on the first electrode subsequently.