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    Method for fabricating capacitor of semiconductor device
    2.
    发明授权
    Method for fabricating capacitor of semiconductor device 失效
    制造半导体器件电容器的方法

    公开(公告)号：US07666738B2

    公开(公告)日：2010-02-23

    申请号：US11952767

    申请日：2007-12-07

    申请人： Dong-Woo Shin ,  Hyung-Bok Choi ,  Jong-Min Lee ,  Jin-Woong Kim

    发明人： Dong-Woo Shin ,  Hyung-Bok Choi ,  Jong-Min Lee ,  Jin-Woong Kim

    IPC分类号： H01L21/8242

    CPC分类号： H01L28/84 ,  H01L21/32155 ,  H01L28/91

    摘要： The present invention relates to a method for fabricating a capacitor of a semiconductor device. The method includes the steps of: forming a first amorphous silicon layer doped with an impurity in a predetermined first doping concentration suppressing dopants from locally agglomerating; forming an impurity undoped second amorphous silicon layer on the first amorphous silicon layer in an in-situ condition; forming a storage node by patterning the first amorphous silicon layer and the second amorphous silicon layer; forming silicon grains on a surface of the storage node; and doping the impurity to the storage node and the silicon grains until reaching a second predetermined concentration for providing conductivity required by the storage node.

    摘要翻译： 本发明涉及半导体器件的电容器的制造方法。 该方法包括以下步骤：在预定的第一掺杂浓度抑制掺杂剂中形成掺杂有杂质的第一非晶硅层局部凝聚; 在原位条件下在第一非晶硅层上形成杂质未掺杂的第二非晶硅层; 通过图案化所述第一非晶硅层和所述第二非晶硅层来形成存储节点; 在所述存储节点的表面上形成硅晶粒; 以及将杂质掺杂到存储节点和硅晶粒直到达到第二预定浓度以提供存储节点所需的导电性。

    Method for fabricating capacitor of semiconductor device
    3.
    发明授权
    Method for fabricating capacitor of semiconductor device 有权
    制造半导体器件电容器的方法

    公开(公告)号：US07407854B2

    公开(公告)日：2008-08-05

    申请号：US10749775

    申请日：2003-12-30

    申请人： Dong-Woo Shin ,  Hyung-Bok Choi ,  Jong-Min Lee ,  Jin-Woong Kim

    发明人： Dong-Woo Shin ,  Hyung-Bok Choi ,  Jong-Min Lee ,  Jin-Woong Kim

    IPC分类号： H01L21/8242

    CPC分类号： H01L28/84 ,  H01L21/32155 ,  H01L28/91

    摘要： The present invention relates to a method for fabricating a capacitor of a semiconductor device. The method includes the steps of: forming a first amorphous silicon layer doped with an impurity in a predetermined first doping concentration suppressing dopants from locally agglomerating; forming an impurity undoped second amorphous silicon layer on the first amorphous silicon layer in an in-situ condition; forming a storage node by patterning the first amorphous silicon layer and the second amorphous silicon layer; forming silicon grains on a surface of the storage node; and doping the impurity to the storage node and the silicon grains until reaching a second predetermined concentration for providing conductivity required by the storage node.

    摘要翻译： 本发明涉及半导体器件的电容器的制造方法。 该方法包括以下步骤：在预定的第一掺杂浓度抑制掺杂剂中形成掺杂有杂质的第一非晶硅层局部凝聚; 在原位条件下在第一非晶硅层上形成杂质未掺杂的第二非晶硅层; 通过图案化所述第一非晶硅层和所述第二非晶硅层来形成存储节点; 在所述存储节点的表面上形成硅晶粒; 以及将杂质掺杂到存储节点和硅晶粒直到达到第二预定浓度以提供存储节点所需的导电性。

    METHOD FOR FABRICATING CAPACITOR OF SEMICONDUCTOR DEVICE
    4.
    发明申请
    METHOD FOR FABRICATING CAPACITOR OF SEMICONDUCTOR DEVICE 失效
    用于制造半导体器件电容器的方法

    公开(公告)号：US20080076231A1

    公开(公告)日：2008-03-27

    申请号：US11952767

    申请日：2007-12-07

    申请人： Dong-Woo SHIN ,  Hyung-Bok Choi ,  Jong-Min Lee ,  Jin-Woong Kim

    发明人： Dong-Woo SHIN ,  Hyung-Bok Choi ,  Jong-Min Lee ,  Jin-Woong Kim

    IPC分类号： H01L21/22

    CPC分类号： H01L28/84 ,  H01L21/32155 ,  H01L28/91

    摘要： The present invention relates to a method for fabricating a capacitor of a semiconductor device. The method includes the steps of: forming a first amorphous silicon layer doped with an impurity in a predetermined first doping concentration suppressing dopants from locally agglomerating; forming an impurity undoped second amorphous silicon layer on the first amorphous silicon layer in an in-situ condition; forming a storage node by patterning the first amorphous silicon layer and the second amorphous silicon layer; forming silicon grains on a surface of the storage node; and doping the impurity to the storage node and the silicon grains until reaching a second predetermined concentration for providing conductivity required by the storage node.

    摘要翻译： 本发明涉及半导体器件的电容器的制造方法。 该方法包括以下步骤：在预定的第一掺杂浓度抑制掺杂剂中形成掺杂有杂质的第一非晶硅层局部凝聚; 在原位条件下在第一非晶硅层上形成杂质未掺杂的第二非晶硅层; 通过图案化所述第一非晶硅层和所述第二非晶硅层来形成存储节点; 在所述存储节点的表面上形成硅晶粒; 以及将杂质掺杂到存储节点和硅晶粒直到达到第二预定浓度以提供存储节点所需的导电性。

    CAPACITOR STRUCTURES, DECOUPLING STRUCTURES AND SEMICONDUCTOR DEVICES INCLUDING THE SAME
    8.
    发明申请
    CAPACITOR STRUCTURES, DECOUPLING STRUCTURES AND SEMICONDUCTOR DEVICES INCLUDING THE SAME 有权
    电容器结构，分解结构和包括其中的半导体器件

    公开(公告)号：US20160073502A1

    公开(公告)日：2016-03-10

    申请号：US14732278

    申请日：2015-06-05

    申请人： Jong-Min Lee ,  Jongryul Jun ,  Eun A Kim ,  Jung-Bum Lim

    发明人： Jong-Min Lee ,  Jongryul Jun ,  Eun A Kim ,  Jung-Bum Lim

    IPC分类号： H05K1/16

    CPC分类号： H01L28/90 ,  H01L27/0805 ,  H01L27/10808 ,  H01L27/10817 ,  H01L27/10847 ,  H01L27/10852 ,  H01L28/82 ,  H01L28/86 ,  H01L28/88 ,  H01L28/92

    摘要： Decoupling structures are provided. The decoupling structures may include first conductive patterns, second conductive patterns and a unitary supporting structure that structurally supports the first conductive patterns and the second conductive patterns. The decoupling structures may also include a common electrode disposed between ones of the first conductive patterns and between ones of the second conductive patterns. The first conductive patterns and the common electrode are electrodes of a first capacitor, and the second conductive patterns and the common electrode are electrodes of a second capacitor. The unitary supporting structure may include openings when viewed from a plan perspective. The first conductive patterns and the second conductive patterns are horizontally spaced apart from each other with a separation region therebetween, and none of the openings extend into the separation region.

    摘要翻译： 提供去耦结构。 去耦结构可以包括第一导电图案，第二导电图案和结构上支撑第一导电图案和第二导电图案的整体支撑结构。 去耦结构还可以包括设置在第一导电图案之间和第二导电图案之间的公共电极。 第一导电图案和公共电极是第一电容器的电极，第二导电图案和公共电极是第二电容器的电极。 从平面图看，整体支撑结构可以包括开口。 第一导电图案和第二导电图案在其间具有分离区域彼此水平间隔开，并且没有一个开口延伸到分离区域中。

    Semiconductor memory devices including an air gap and methods of fabricating the same
    9.
    发明授权
    Semiconductor memory devices including an air gap and methods of fabricating the same 有权
    包括气隙的半导体存储器件及其制造方法

    公开(公告)号：US09166012B2

    公开(公告)日：2015-10-20

    申请号：US14096195

    申请日：2013-12-04

    申请人： Jae-Hwang Sim ,  Jinhyun Shin ,  Jong-Min Lee

    发明人： Jae-Hwang Sim ,  Jinhyun Shin ,  Jong-Min Lee

    IPC分类号： H01L29/788 ,  H01L29/423 ,  H01L21/764 ,  H01L27/115

    CPC分类号： H01L27/11524 ,  H01L21/764 ,  H01L29/42324

    摘要： Provided are a semiconductor memory device and a method of fabricating the same, the semiconductor memory device may include a semiconductor substrate with a first trench defining active regions in a first region and a second trench provided in a second region around the first region, a gate electrode provided on the first region to cross the active regions, a charge storing pattern disposed between the gate electrode and the active regions, a blocking insulating layer provided between the gate electrode and the charge storing pattern and extending over the first trench to define a first air gap in the first trench, and an insulating pattern provided spaced apart from a bottom surface of the second trench to define a second air gap in the second trench.

    摘要翻译： 提供一种半导体存储器件及其制造方法，半导体存储器件可以包括半导体衬底，该半导体衬底具有限定第一区域中的有源区域的第一沟槽和设置在第一区域周围的第二区域中的第二沟槽，栅极 电极，设置在第一区域上以与有源区交叉，设置在栅电极和有源区之间的电荷存储图案，设置在栅电极和电荷存储图案之间并在第一沟槽上延伸以限定第一 第一沟槽中的空气间隙，以及设置成与第二沟槽的底表面间隔开的绝缘图案，以在第二沟槽中限定第二气隙。

    Display device and a method of manufacturing the same
    10.
    发明授权
    Display device and a method of manufacturing the same 有权
    显示装置及其制造方法

    公开(公告)号：US08617910B2

    公开(公告)日：2013-12-31

    申请号：US13239822

    申请日：2011-09-22

    申请人： Jae-Han Lee ,  Jong-Min Lee ,  Sun-Kyu Son ,  Young-Il Ban ,  Ok-Kwon Shin

    发明人： Jae-Han Lee ,  Jong-Min Lee ,  Sun-Kyu Son ,  Young-Il Ban ,  Ok-Kwon Shin

    IPC分类号： H01L21/00 ,  H01L29/18 ,  H05K7/00

    CPC分类号： G02F1/13452

    摘要： A display device includes an array substrate, a driving film and an adhesive member. The array substrate includes a first base substrate, a plurality of first signal pads formed on the first base substrate and a first dummy pad formed adjacent to the first signal pads. The driving film includes a base film, a plurality of output terminals formed on the base film and a first alignment mark formed adjacent to the output terminals. The adhesive member adheres the first signal pads to the output terminals, and adheres the first dummy pad to the first alignment mark.

    摘要翻译： 显示装置包括阵列基板，驱动膜和粘合构件。 阵列基板包括第一基底基板，形成在第一基底基板上的多个第一信号焊盘和邻近第一信号焊盘形成的第一虚设焊盘。 驱动膜包括基膜，形成在基膜上的多个输出端子和邻近输出端子形成的第一对准标记。 粘合剂粘合第一信号垫到输出端，并将第一虚拟垫粘附到第一对准标记。