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    Semiconductor memory devices utilizing randomization and data programming methods thereof
    1.
    发明授权
    Semiconductor memory devices utilizing randomization and data programming methods thereof 有权
    利用其随机化和数据编程方法的半导体存储器件

    公开(公告)号：US09136002B2

    公开(公告)日：2015-09-15

    申请号：US14242406

    申请日：2014-04-01

    Applicant: Yongkyu Lee ,  BoGeun Kim

    Inventor： Yongkyu Lee ,  BoGeun Kim

    IPC: G11C16/04 ,  G11C16/10 ,  G11C11/56 ,  G11C16/34 ,  G11C7/02 ,  G11C7/10

    CPC classification number: G11C16/10 ,  G11C7/02 ,  G11C7/1006 ,  G11C11/5628 ,  G11C16/3418

    Abstract: A data programming method of a semiconductor memory device is provided which includes randomizing write data using a randomization method selected from among a plurality of randomization methods according to whether the write data is programmed in one of a plurality of nonvolatile memories; and programming the randomized write data in at least one of the plurality of nonvolatile memories, wherein the plurality of nonvolatile memories has different types from one another.

    Abstract translation: 提供一种半导体存储器件的数据编程方法，其包括使用根据所述写入数据是否被编程在多个非易失性存储器之一中的从多种随机化方法中选择的随机化方法来随机化写入数据; 以及将所述随机写入数据编程在所述多个非易失性存储器中的至少一个中，其中所述多个非易失性存储器具有彼此不同的类型。

    Embedded Semiconductor Device Including Phase Changeable Random Access Memory Element and Method of Fabricating the Same
    2.
    发明申请
    Embedded Semiconductor Device Including Phase Changeable Random Access Memory Element and Method of Fabricating the Same 审中-公开
    包括相变随机存取存储器元件的嵌入式半导体器件及其制造方法

    公开(公告)号：US20120214262A1

    公开(公告)日：2012-08-23

    申请号：US13401550

    申请日：2012-02-21

    Applicant: Teakwang Yu ,  Yongtae Kim ,  Byungsup Shim ,  Yongkyu Lee

    Inventor： Teakwang Yu ,  Yongtae Kim ,  Byungsup Shim ,  Yongkyu Lee

    IPC: H01L21/66

    CPC classification number: H01L27/101 ,  H01L22/14 ,  H01L22/20 ,  H01L27/088 ,  H01L27/1026 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144

    Abstract: Disclosed are an embedded semiconductor device including a phase changeable random access memory element and a method of fabricating the same. A semiconductor chip including a main memory element and a supplementary memory element is integrated on a substrate, intrinsic chip data are obtained by electrically testing the semiconductor chip, and the semiconductor chip is packaged. The intrinsic chip data are written into the supplementary memory element before the packaging of the semiconductor chip, and a memory layer of the supplementary memory element is formed of a material exhibiting an improved data retention property under thermal environmental conditions as compared with a memory layer of the main memory element.

    Abstract translation: 公开了一种包括相变随机存取存储元件的嵌入式半导体器件及其制造方法。 将包括主存储元件和补充存储元件的半导体芯片集成在基板上，通过电测试半导体芯片来获得本征芯片数据，并且封装半导体芯片。 在半导体芯片的封装之前，本征芯片数据被写入辅助存储元件中，并且辅助存储元件的存储层与在热环境条件下具有改善的数据保持性能的材料相比，与存储层 主要内存元素。

    METHOD FOR FORMING A HARD MASK PATTERN AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE USING THE SAME
    3.
    发明申请
    METHOD FOR FORMING A HARD MASK PATTERN AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE USING THE SAME 有权
    用于形成硬掩模图案的方法和使用其制造半导体器件的方法

    公开(公告)号：US20170040531A1

    公开(公告)日：2017-02-09

    申请号：US15179971

    申请日：2016-06-10

    Applicant: Yong-Seok CHUNG ,  YOONJONG SONG ,  YONGKYU LEE ,  GWANHYEOB KOH

    Inventor： Yong-Seok CHUNG ,  YOONJONG SONG ,  YONGKYU LEE ,  GWANHYEOB KOH

    IPC: H01L43/12 ,  H01L21/027 ,  H01L21/266

    CPC classification number: H01L43/12 ,  H01L21/0273 ,  H01L21/266 ,  H01L27/228

    Abstract: The inventive concepts provide a method for forming a hard mask pattern. The method includes forming a hard mask layer on an etch target layer disposed on a substrate, forming a photoresist pattern having an opening exposing one region of the hard mask layer, performing an oxygen ion implantation process on the one region using the photoresist pattern as a mask to form an oxidized portion in the one region, and patterning the hard mask layer using the oxidized portion as an etch mask.

    Abstract translation: 本发明构思提供了形成硬掩模图案的方法。 该方法包括在设置在基板上的蚀刻目标层上形成硬掩模层，形成具有暴露硬掩模层的一个区域的开口的光致抗蚀剂图案，使用光致抗蚀剂图案作为一个区域对该区域进行氧离子注入工艺 在一个区域中形成氧化部分，并使用氧化部分作为蚀刻掩模对硬掩模层进行构图。

    Semiconductor memory device
    4.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US09401385B2

    公开(公告)日：2016-07-26

    申请号：US14639183

    申请日：2015-03-05

    Applicant: Boyoung Seo ,  Yongkyu Lee ,  Keemoon Chun

    Inventor： Boyoung Seo ,  Yongkyu Lee ,  Keemoon Chun

    IPC: H01L29/66 ,  H01L29/82 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  G11C11/16

    CPC classification number: H01L27/228 ,  G11C11/161 ,  G11C11/1655 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  H01L43/02 ,  H01L43/08

    Abstract: The inventive concepts provide a semiconductor memory device including variable resistance memory elements. The semiconductor memory device may include a first bit line disposed at a first height from a semiconductor substrate, a second bit line disposed at a second height, which is different from the first height, from the semiconductor substrate, a first variable resistance memory element connected to the first bit line, and a second variable resistance memory element connected to the second bit line. The first and second variable resistance memory elements may be disposed at substantially the same height from the semiconductor substrate.

    Abstract translation: 本发明构思提供了包括可变电阻存储器元件的半导体存储器件。 半导体存储器件可以包括设置在距离半导体衬底的第一高度处的第一位线，与半导体衬底相比设置在与第一高度不同的第二高度的第二位线，连接到第一可变电阻存储器元件 到第一位线，以及连接到第二位线的第二可变电阻存储元件。 第一和第二可变电阻存储器元件可以设置在与半导体衬底基本相同的高度处。

    Magnetic memory devices
    8.
    发明授权
    Magnetic memory devices 有权

    公开(公告)号：US10269401B2

    公开(公告)日：2019-04-23

    申请号：US15294100

    申请日：2016-10-14

    Applicant: Boyoung Seo ,  Seongui Seo ,  Gwanhyeob Koh ,  Yongkyu Lee

    Inventor： Boyoung Seo ,  Seongui Seo ,  Gwanhyeob Koh ,  Yongkyu Lee

    IPC: G11C11/16 ,  H01L27/22

    Abstract: A magnetic memory device includes a substrate, a landing pad on the substrate, first and second magnetic tunnel junction patterns disposed on the interlayer insulating layer and spaced apart from the landing pad when viewed from a plan view, and an interconnection structure electrically connecting a top surface of the second magnetic tunnel junction pattern to the landing pad. A distance between the landing pad and the first magnetic tunnel junction pattern is greater than a distance between the first and second magnetic tunnel junction patterns, and a distance between the landing pad and the second magnetic tunnel junction pattern is greater than the distance between the first and second magnetic tunnel junction patterns, when viewed from a plan view.

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