公开(公告)号：US20050246498A1

公开(公告)日：2005-11-03

申请号：US10512699

申请日：2003-03-03

申请人： Doron Schupper ,  Yakov Tokar ,  Jacob Efrat

发明人： Doron Schupper ,  Yakov Tokar ,  Jacob Efrat

IPC分类号： A01M1/14 ,  A01M1/24 ,  G06F12/08 ,  G06F12/00

CPC分类号： G06F12/0859 ,  A01M1/14 ,  A01M1/24 ,  A01M2200/011 ,  A01M2200/012 ,  G06F12/0851 ,  G06F12/1045

摘要： Read/write conflicts in an instruction cache memory (11) are reduced by configuring the memory as two even and odd array sub-blocks (12,13) and adding an input buffer (10) between the memory (11) and an update (16). Contentions between a memory read and a memory write are minimised by the buffer (10) shifting the update sequence with respect to the read sequence. The invention can adapt itself for use in digital signal processing systems with different external memory behaviour as far as latency and burst capability is concerned.

摘要翻译： 通过将存储器配置为两个偶数和奇数阵列子块（12,13）并在存储器（11）和更新（12,13）之间增加一个输入缓冲器（10））来减少指令高速缓冲存储器（11）中的读/写冲突 16）。 通过缓冲器（10）将更新序列相对于读取序列移位来使存储器读取和存储器写入之间的争用最小化。 本发明可以适应于具有不同外部存储器行为的数字信号处理系统，只要涉及延迟和突发能力。

公开(公告)号：US06848030B2

公开(公告)日：2005-01-25

申请号：US09909562

申请日：2001-07-20

申请人： Yakov Tokar ,  Amit Gur ,  Jacob Efrat ,  Doron Schupper

发明人： Yakov Tokar ,  Amit Gur ,  Jacob Efrat ,  Doron Schupper

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/0862

摘要： A processing system has a processor, a cache, and a fetch unit. If there is a miss in the cache, the fetch unit generates a fetch address for the miss in the cache for the purpose of retrieving the requested data from external memory and providing the data to the processor and loading the data in a location in a line in the cache. The fetch unit also generates additional prefetch addresses for addresses consecutive with the fetch address. The prefetch addresses continue to be generated for all of the locations in the line in the cache that are consecutive with the fetch address. The generation of prefetch addresses will be stopped if another requests arrives that is not part of the already generated prefetched addresses. Further, the outstanding prefetches will be terminated if the external memory can handle such termination.

摘要翻译： 处理系统具有处理器，高速缓存和提取单元。 如果高速缓存中存在缺失，则提取单元为缓存中的未命中生成提取地址，以便从外部存储器检索所请求的数据，并将数据提供给处理器并将数据加载到一行中的位置 在缓存中。 提取单元还生成与获取地址连续的地址的附加预取地址。 对于与提取地址连续的高速缓存中的行中的所有位置，继续生成预取地址。 如果另一个请求到达不是已经生成的预取地址的一部分，则预取地址的生成将被停止。 此外，如果外部存储器可以处理这种终止，那么未完成的预取将被终止。

公开(公告)号：US09436624B2

公开(公告)日：2016-09-06

申请号：US13952092

申请日：2013-07-26

申请人： Ziv Zamsky ,  Moshe Anschel ,  Itay Keidar ,  Itay S. Peled ,  Doron Schupper ,  Yakov Tokar

发明人： Ziv Zamsky ,  Moshe Anschel ,  Itay Keidar ,  Itay S. Peled ,  Doron Schupper ,  Yakov Tokar

IPC分类号： G06F13/14 ,  G06F3/00 ,  G06F13/16

CPC分类号： G06F13/16

摘要： A circuitry for a computing system comprising a first load/store unit, LSU, and a second LSU as well as a memory arrangement. The first LSU is connected to the memory arrangement via a first bus arrangement comprising a first write bus and a first read bus. The second LSU is connected to the memory arrangement via a second bus arrangement comprising a second write bus and a second read bus. The computing system is arranged to carry out a multiple load instruction to read data via the first read bus and the second read bus and/or to carry out a multiple store instruction to write data via the first write bus and the second write bus.

摘要翻译： 一种用于计算系统的电路，包括第一加载/存储单元，LSU和第二LSU以及存储器装置。 第一LSU经由包括第一写总线和第一读总线的第一总线装置连接到存储器装置。 第二LSU经由包括第二写总线和第二读总线的第二总线装置连接到存储器装置。 计算系统被配置为执行多重加载指令以经由第一读取总线和第二读取总线读取数据和/或执行多个存储指令以经由第一写入总线和第二写入总线写入数据。

公开(公告)号：US20100049954A1

公开(公告)日：2010-02-25

申请号：US12194279

申请日：2008-08-19

申请人： Guy Shmueli ,  Itzhak Barak ,  Uri Dayan ,  Amir Paran ,  Idan Rozenberg ,  Doron Schupper

发明人： Guy Shmueli ,  Itzhak Barak ,  Uri Dayan ,  Amir Paran ,  Idan Rozenberg ,  Doron Schupper

IPC分类号： G06F9/22

CPC分类号： G06F9/3842 ,  G06F9/30094

摘要： A method for speculative execution of instructions, the method includes: decoding a compare instruction; speculatively executing, in a continuous manner, conditional instructions that are conditioned by a condition that is related to a resolution of the compare instruction and are decoded during a speculation window that starts at the decoding of the compare instruction and ends when the compare instruction is resolved; and stalling an execution of a non-conditional instruction that is dependent upon an outcome of at least one of the conditional instructions, until the speculation window ends.

摘要翻译： 一种用于推测执行指令的方法，所述方法包括：对比较指令进行解码; 以连续的方式推测性地执行由与比较指令的分辨率相关的条件调节的条件指令，并且在比较指令的解码开始的推测窗口期间被解码，并且当比较指令被解析时结束 ; 并且停止依赖于至少一个条件指令的结果的非条件指令的执行，直到投机窗口结束为止。

公开(公告)号：US09934035B2

公开(公告)日：2018-04-03

申请号：US14778093

申请日：2013-03-21

申请人： Uri Dayan ,  Erez Arbel-Meirovich ,  Liron Artsi ,  Doron Schupper

发明人： Uri Dayan ,  Erez Arbel-Meirovich ,  Liron Artsi ,  Doron Schupper

IPC分类号： G06F9/30 ,  G06F11/34 ,  G06N5/00 ,  G06F11/36

CPC分类号： G06F9/30058 ,  G06F9/30072 ,  G06F9/30145 ,  G06F11/348 ,  G06F11/3636 ,  G06N5/003

摘要： A data processing device for executing a program is described. The program comprises one or more instruction groups and one or more predicates, each instruction group comprising one or more instructions. The data processing device comprises a processing unit and a trace unit connected to or integrated in the processing unit. The trace unit generates a predicate trace for tracing the values of the one or more predicates. The processing unit executes, in each of a series of execution periods, one of the instruction groups and updated the values of none, one, or more of the predicates in dependence on the respective instruction group. The trace unit appends the updated values of the none, one, or more predicates to the predicate trace and does not append any non-updated values of the predicates.A method of reporting predicate values and a data carrier are also disclosed.

公开(公告)号：US08266414B2

公开(公告)日：2012-09-11

申请号：US12194286

申请日：2008-08-19

申请人： Lev Vaskevich ,  Itzhak Barak ,  Amir Paran ,  Yuval Peled ,  Idan Rozenberg ,  Doron Schupper

发明人： Lev Vaskevich ,  Itzhak Barak ,  Amir Paran ,  Yuval Peled ,  Idan Rozenberg ,  Doron Schupper

IPC分类号： G06F9/40

CPC分类号： G06F9/325 ,  G06F9/381

摘要： A method for managing a hardware instruction loop, the method includes: (i) detecting, by a branch prediction unit, an instruction loop; wherein a size of the instruction loop exceeds a size of a storage space allocated in a fetch unit for storing fetched instructions; (ii) requesting from the fetch unit to fetch instructions of the instruction loop that follow the first instructions of the instruction loop; and (iii) selecting, during iterations of the instruction loop, whether to provide to a dispatch unit one of the first instructions of the instruction loop or another instruction that is fetched by the fetch unit; wherein the first instructions of the instruction loop are stored at the dispatch unit.

摘要翻译： 一种用于管理硬件指令循环的方法，所述方法包括：（i）由分支预测单元检测指令循环; 其中所述指令循环的大小超过在用于存储获取的指令的获取单元中分配的存储空间的大小; （ii）从提取单元请求获取遵循指令循环的第一指令的指令循环的指令; 以及（iii）在所述指令循环的迭代期间选择是否向所述调度单元提供所述指令循环的所述第一指令之一或由所述提取单元获取的另一指令; 其中指令循环的第一指令被存储在调度单元中。

公开(公告)号：US20140019990A1

公开(公告)日：2014-01-16

申请号：US14006022

申请日：2011-03-30

申请人： Doron Schupper ,  Itzhak Barak ,  Uri Dayan ,  Noam Eshel-Goldman ,  Lev Vaskevich

发明人： Doron Schupper ,  Itzhak Barak ,  Uri Dayan ,  Noam Eshel-Goldman ,  Lev Vaskevich

IPC分类号： G06F9/46

CPC分类号： G06F9/461 ,  G06F9/3004 ,  G06F9/30076 ,  G06F9/30123 ,  G06F9/30145 ,  G06F9/30185 ,  G06F9/462

摘要： An integrated circuit device comprising an instruction processing module for performing operations on data in accordance with received instructions. The instruction processing module comprises a context selector unit arranged to selectively provide access to at least one process attribute(s) within a plurality of process contexts in accordance with at least one context selector value received thereby. The instruction processing module is arranged to receive an instruction comprising a context indication for a process attribute with which an operation is to be performed, provide the context selector value based at least partly on the context indication to the context selector unit, and execute the operation to be performed with the process attribute for at least one process context to which the context selector unit provides access in accordance with the context selector value.

摘要翻译： 一种集成电路装置，包括用于根据接收到的指令对数据执行操作的指令处理模块。 指令处理模块包括上下文选择器单元，其被布置为根据从其接收的至少一个上下文选择器值来选择性地提供对多个进程上下文中的至少一个进程属性的访问。 指令处理模块被配置为接收包括用于要执行操作的处理属性的上下文指示的指令，至少部分地基于上下文指示将上下文选择器值提供给上下文选择器单元，并且执行操作 用于根据上下文选择器值为上下文选择器单元提供访问的至少一个处理上下文的过程属性执行。

公开(公告)号：US07930522B2

公开(公告)日：2011-04-19

申请号：US12194279

申请日：2008-08-19

申请人： Guy Shumeli ,  Itzhak Barak ,  Uri Dayan ,  Amir Paran ,  Idan Rozenberg ,  Doron Schupper

发明人： Guy Shumeli ,  Itzhak Barak ,  Uri Dayan ,  Amir Paran ,  Idan Rozenberg ,  Doron Schupper

IPC分类号： G06F9/48

CPC分类号： G06F9/3842 ,  G06F9/30094

摘要： A method for speculative execution of instructions, the method includes: decoding a compare instruction; speculatively executing, in a continuous manner, conditional instructions that are conditioned by a condition that is related to a resolution of the compare instruction and are decoded during a speculation window that starts at the decoding of the compare instruction and ends when the compare instruction is resolved; and stalling an execution of a non-conditional instruction that is dependent upon an outcome of at least one of the conditional instructions, until the speculation window ends.

摘要翻译： 一种用于推测执行指令的方法，所述方法包括：对比较指令进行解码; 以连续的方式推测性地执行由与比较指令的分辨率相关的条件调节的条件指令，并且在比较指令的解码开始的推测窗口期间被解码并且当比较指令被解析时结束 ; 并且停止依赖于至少一个条件指令的结果的非条件指令的执行，直到投机窗口结束为止。

公开(公告)号：US20130326200A1

公开(公告)日：2013-12-05

申请号：US13982854

申请日：2011-02-11

申请人： Amir Kleen ,  Itzhak Barak ,  Yuval Peled ,  Idan Rozenberg ,  Doron Schupper

发明人： Amir Kleen ,  Itzhak Barak ,  Yuval Peled ,  Idan Rozenberg ,  Doron Schupper

IPC分类号： G06F9/30

CPC分类号： G06F9/30043 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3861

摘要： An integrated circuit device comprising at least one instruction processing module arranged to compare validation data with data stored within a target register upon receipt of a load validation instruction. Wherein, the instruction processing module is further arranged to proceed with execution of a next sequential instruction if the validation data matches the stored data within the target register, and to load the validation data into the target register if the validation data does not match the stored data within the target register.

摘要翻译： 一种集成电路装置，包括至少一个指令处理模块，其被布置为在接收到负载验证指令时将验证数据与存储在目标寄存器内的数据进行比较。 其中，所述指令处理模块还被布置成如果所述验证数据与所述目标寄存器中存储的数据匹配，则继续执行下一个顺序指令，并且如果所述验证数据与所存储的所述存储的数据不匹配，则将所述验证数据加载到所述目标寄存器中 目标寄存器内的数据。

公开(公告)号：US20130290686A1

公开(公告)日：2013-10-31

申请号：US13977082

申请日：2011-01-21

申请人： Yuval Peled ,  Itzhak Barak ,  Idan Rozenberg ,  Doron Schupper ,  Lev Vaskevich

发明人： Yuval Peled ,  Itzhak Barak ,  Idan Rozenberg ,  Doron Schupper ,  Lev Vaskevich

IPC分类号： G06F9/30 ,  G06F7/57

CPC分类号： G06F9/3001 ,  G06F7/57 ,  G06F9/30029 ,  G06F9/30072 ,  G06F9/30094

摘要： An integrated circuit device comprises at least one instruction processing module arranged to perform branch predication. The at least one instruction processing module comprises at least one predicate calculation module arranged to receive as an input at least one result vector for a predicate function and at least one conditional parameter value therefor and output a predicate result value from the at least one result vector based at least partly on the at least one received conditional parameter value.

摘要翻译： 集成电路装置包括布置成执行分支预测的至少一个指令处理模块。 所述至少一个指令处理模块包括至少一个谓词计算模块，被布置为接收用于谓词函数的至少一个结果向量作为输入，以及至少一个条件参数值，并从所述至少一个结果向量输出谓词结果值 至少部分地基于所述至少一个接收到的条件参数值。