公开(公告)号：US08466501B2

公开(公告)日：2013-06-18

申请号：US12784583

申请日：2010-05-21

申请人： Douglas B. Hershberger ,  Richard A. Phelps ,  Robert M. Rassel ,  Stephen A. St. Onge ,  Michael J. Zierak

发明人： Douglas B. Hershberger ,  Richard A. Phelps ,  Robert M. Rassel ,  Stephen A. St. Onge ,  Michael J. Zierak

IPC分类号： H01L29/808

CPC分类号： G06F17/5068 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0843 ,  H01L29/66901 ,  H01L29/8086

摘要： An asymmetric silicon-on-insulator (SOI) junction field effect transistor (JFET) and a method. The JFET includes a bottom gate on an insulator layer, a channel region on the bottom gate and, on the channel region, source/drain regions and a top gate between the source/drain regions. STIs isolate the source/drain regions from the top gate and a DTI laterally surrounds the JFET to isolate it from other devices. Non-annular well(s) are positioned adjacent to the channel region and bottom gate (e.g., a well having the same conductivity type as the top and bottom gates can be connected to the top gate and can extend down to the insulator layer, forming a gate contact on only a portion of the channel region, and/or another well having the same conductivity type as the channel and source/drain regions can extend from the source region to the insulator layer, forming a source-to-channel strap).

摘要翻译： 不对称绝缘体上硅（SOI）结场效应晶体管（JFET）及其方法。 JFET包括在绝缘体层上的底栅极，底栅上的沟道区，以及沟道区上的源/漏区和源/漏区之间的顶栅。 STI将源极/漏极区域与顶部栅极隔离，并且DTI横向围绕JFET以将其与其它器件隔离。 非环形阱位于与沟道区域和底部栅极相邻的位置（例如，具有与顶部和底部栅极相同的导电类型的阱可以连接到顶部栅极并且可以向下延伸到绝缘体层，形成 在沟道区域的仅一部分上的栅极接触和/或具有与沟道和源极/漏极区相同的导电类型的另一个阱可以从源极区域延伸到绝缘体层，形成源极至沟道的带） 。

公开(公告)号：US20110284930A1

公开(公告)日：2011-11-24

申请号：US12784583

申请日：2010-05-21

申请人： Douglas B. Hershberger ,  Richard A. Phelps ,  Robert M. Rassel ,  Stephen A. St. Onge ,  Michael J. Zierak

发明人： Douglas B. Hershberger ,  Richard A. Phelps ,  Robert M. Rassel ,  Stephen A. St. Onge ,  Michael J. Zierak

IPC分类号： H01L29/812 ,  H01L21/782 ,  G06F17/50 ,  H01L27/12

CPC分类号： G06F17/5068 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0843 ,  H01L29/66901 ,  H01L29/8086

摘要： An asymmetric silicon-on-insulator (SOI) junction field effect transistor (JFET) and a method. The JFET includes a bottom gate on an insulator layer, a channel region on the bottom gate and, on the channel region, source/drain regions and a top gate between the source/drain regions. STIs isolate the source/drain regions from the top gate and a DTI laterally surrounds the JFET to isolate it from other devices. Non-annular well(s) are positioned adjacent to the channel region and bottom gate (e.g., a well having the same conductivity type as the top and bottom gates can be connected to the top gate and can extend down to the insulator layer, forming a gate contact on only a portion of the channel region, and/or another well having the same conductivity type as the channel and source/drain regions can extend from the source region to the insulator layer, forming a source-to-channel strap).

摘要翻译： 不对称绝缘体上硅（SOI）结场效应晶体管（JFET）及其方法。 JFET包括在绝缘体层上的底栅极，底栅上的沟道区，以及沟道区上的源/漏区和源/漏区之间的顶栅。 STI将源极/漏极区域与顶部栅极隔离，并且DTI横向围绕JFET以将其与其它器件隔离。 非环形阱位于与沟道区域和底部栅极相邻的位置（例如，具有与顶部和底部栅极相同的导电类型的阱可以连接到顶部栅极并且可以向下延伸到绝缘体层，形成 在沟道区域的仅一部分上的栅极接触和/或具有与沟道和源极/漏极区相同的导电类型的另一个阱可以从源极区域延伸到绝缘体层，形成源极至沟道的带） 。

公开(公告)号：US07977714B2

公开(公告)日：2011-07-12

申请号：US11875190

申请日：2007-10-19

申请人： John Ellis-Monaghan ,  Richard A. Phelps ,  Robert M. Rassel ,  Steven H. Voldman ,  Michael J. Zierak

发明人： John Ellis-Monaghan ,  Richard A. Phelps ,  Robert M. Rassel ,  Steven H. Voldman ,  Michael J. Zierak

IPC分类号： H01L29/808 ,  H01L21/337

CPC分类号： H01L29/808 ,  H01L29/1058 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/20 ,  H01L29/22 ,  H01L29/66901 ,  H01L29/66924

摘要： A wrapped gate junction field effect transistor (JFET) with at least one semiconductor channel having a first conductivity type doping is provided. Both sidewalls of each of the at least one semiconductor channel laterally abuts a side gate region having a second conductivity type doping, which is the opposite of the first conductivity doping. Further, the at least one semiconductor channel vertically abuts a top gate region and at least one bottom gate region, both having the second conductivity type doping. The gate electrode, which comprises side gate region, the top gate region, and at least one bottom gate regions, wraps around each of the at least one semiconductor channel to provide tight control of the current, i.e., a low off-current, through the at least one semiconductor channel. By employing multiple channels, the JFET may provide a high on-current.

摘要翻译： 提供具有至少一个具有第一导电类型掺杂的半导体沟道的封装的栅极结场效应晶体管（JFET）。 所述至少一个半导体通道中的每一个的两个侧壁横向邻接具有第二导电类型掺杂的侧栅极区域，其与第一导电掺杂相反。 此外，至少一个半导体沟道垂直邻接顶部栅极区域和至少一个具有第二导电类型掺杂的底部栅极区域。 包括侧栅极区域的栅极电极，顶栅极区域和至少一个底栅极区域围绕至少一个半导体通道中的每一个环绕，以提供电流的严格控制，即，低截止电流，通过 所述至少一个半导体通道。 通过采用多个通道，JFET可以提供高导通电流。

公开(公告)号：US20090101941A1

公开(公告)日：2009-04-23

申请号：US11875190

申请日：2007-10-19

申请人： John Ellis-Monaghan ,  Richard A. Phelps ,  Robert M. Rassel ,  Steven H. Voldman ,  Michael J. Zierak

发明人： John Ellis-Monaghan ,  Richard A. Phelps ,  Robert M. Rassel ,  Steven H. Voldman ,  Michael J. Zierak

IPC分类号： H01L29/808 ,  H01L21/337

CPC分类号： H01L29/808 ,  H01L29/1058 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/20 ,  H01L29/22 ,  H01L29/66901 ,  H01L29/66924

摘要： A wrapped gate junction field effect transistor (JFET) with at least one semiconductor channel having a first conductivity type doping is provided. Both sidewalls of each of the at least one semiconductor channel laterally abuts a side gate region having a second conductivity type doping, which is the opposite of the first conductivity doping. Further, the at least one semiconductor channel vertically abuts a top gate region and at least one bottom gate region, both having the second conductivity type doping. The gate electrode, which comprises side gate region, the top gate region, and at least one bottom gate regions, wraps around each of the at least one semiconductor channel to provide tight control of the current, i.e., a low off-current, through the at least one semiconductor channel. By employing multiple channels, the JFET may provide a high on-current.

摘要翻译： 提供具有至少一个具有第一导电类型掺杂的半导体沟道的封装的栅极结场效应晶体管（JFET）。 所述至少一个半导体通道中的每一个的两个侧壁横向邻接具有第二导电类型掺杂的侧栅极区域，其与第一导电掺杂相反。 此外，至少一个半导体沟道垂直邻接顶部栅极区域和至少一个具有第二导电类型掺杂的底部栅极区域。 包括侧栅极区域的栅极电极，顶栅极区域和至少一个底栅极区域围绕至少一个半导体通道中的每一个环绕，以提供电流的严格控制，即，低截止电流，通过 所述至少一个半导体通道。 通过采用多个通道，JFET可以提供高导通电流。

公开(公告)号：US08168500B2

公开(公告)日：2012-05-01

申请号：US13013311

申请日：2011-01-25

申请人： John B. Campi ,  Richard A. Phelps ,  Robert M. Rassel ,  Michael J. Zierak

发明人： John B. Campi ,  Richard A. Phelps ,  Robert M. Rassel ,  Michael J. Zierak

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L29/7838 ,  H01L21/26586 ,  H01L29/0653 ,  H01L29/0688 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/66659

摘要： A metal-oxide-semiconductor field effect transistor (MOSFET) has a body layer that follows the contour of exposed surfaces of a semiconductor substrate and contains a bottom surface of a shallow trench and adjoined sidewalls. A bottom electrode layer vertically abuts the body layer and provides an electrical bias to the body layer. A top electrode and source and drain regions are formed on the body layer. The thickness of the body layer is selected to allow full depletion of the body layer by the top electrode and a bottom electrode layer. The portion of the body layer underneath the shallow trench extends the length of a channel to enable a high voltage operation. Further, the MOSFET provides a double gate configuration and a tight control of the channel to enable a complete pinch-off of the channel and a low off-current in a compact volume.

摘要翻译： 金属氧化物半导体场效应晶体管（MOSFET）具有跟随半导体衬底的暴露表面的轮廓的主体层，并且包含浅沟槽的底表面和相邻的侧壁。 底部电极层垂直邻接体层并向身体层提供电偏压。 顶部电极和源极和漏极区域形成在主体层上。 选择体层的厚度以允许顶层电极和底电极层完全耗尽体层。 浅沟槽下面的体层的部分延伸通道的长度以实现高电压操作。 此外，MOSFET提供双栅极配置和通道的严格控制，以实现通道的完全夹断和紧凑体积中的低截止电流。

公开(公告)号：US07943445B2

公开(公告)日：2011-05-17

申请号：US12388586

申请日：2009-02-19

申请人： Frederick G. Anderson ,  David S. Collins ,  Richard A. Phelps ,  Robert M. Rassel ,  Michael J. Zierak

发明人： Frederick G. Anderson ,  David S. Collins ,  Richard A. Phelps ,  Robert M. Rassel ,  Michael J. Zierak

IPC分类号： H01L21/00 ,  H01L21/336

CPC分类号： H01L29/1058 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0843 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/20 ,  H01L29/22 ,  H01L29/66901 ,  H01L29/808

摘要： A junction field effect transistor (JFET) in a semiconductor substrate includes a source region, a drain region, a channel region, an upper gate region, and a lower gate region. The lower gate region is electrically connected to the upper gate region. The upper and lower gate regions control the current flow through the channel region. By performing an ion implantation step that extends the thickness of the source region to a depth greater than the thickness of the drain region, an asymmetric JFET is formed. The extension of depth of the source region relative to the depth of the drain region reduces the length for minority charge carriers to travel through the channel region, reduces the on-resistance of the JFET, and increases the on-current of the JFET, thereby enhancing the overall performance of the JFET without decreasing the allowable Vds or dramatically increasing Voff/Vpinch.

摘要翻译： 半导体衬底中的结型场效应晶体管（JFET）包括源极区，漏极区，沟道区，上部栅极区域和下部栅极区域。 下栅极区域电连接到上栅极区域。 上下栅极区域控制通过沟道区域的电流。 通过执行将源极区域的厚度延伸到大于漏极区域的厚度的深度的离子注入步骤，形成非对称JFET。 源极区域相对于漏极区域的深度的深度的扩展减小了少数电荷载流子穿过沟道区域的长度，减小了JFET的导通电阻，并增加了JFET的导通电流，由此 提高JFET的整体性能，而不会降低容许的Vds或显着增加Voff / Vpinch。

公开(公告)号：US20090179272A1

公开(公告)日：2009-07-16

申请号：US11972811

申请日：2008-01-11

申请人： John B. Campi, JR. ,  Richard A. Phelps ,  Robert M. Rassel ,  Michael J. Zierak

发明人： John B. Campi, JR. ,  Richard A. Phelps ,  Robert M. Rassel ,  Michael J. Zierak

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7838 ,  H01L21/26586 ,  H01L29/0653 ,  H01L29/0688 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/66659

摘要： A metal-oxide-semiconductor field effect transistor (MOSFET) has a body layer that follows the contour of exposed surfaces of a semiconductor substrate and contains a bottom surface of a shallow trench and adjoined sidewalls. A bottom electrode layer vertically abuts the body layer and provides an electrical bias to the body layer. A top electrode and source and drain regions are formed on the body layer. The thickness of the body layer is selected to allow full depletion of the body layer by the top electrode and a bottom electrode layer. The portion of the body layer underneath the shallow trench extends the length of a channel to enable a high voltage operation. Further, the MOSFET provides a double gate configuration and a tight control of the channel to enable a complete pinch-off of the channel and a low off-current in a compact volume.

摘要翻译： 金属氧化物半导体场效应晶体管（MOSFET）具有跟随半导体衬底的暴露表面的轮廓的主体层，并且包含浅沟槽的底表面和相邻的侧壁。 底部电极层垂直邻接体层并向身体层提供电偏压。 顶部电极和源极和漏极区域形成在主体层上。 选择体层的厚度以允许顶层电极和底电极层完全耗尽体层。 浅沟槽下面的体层的部分延伸通道的长度以实现高电压操作。 此外，MOSFET提供双栅极配置和通道的严格控制，以实现通道的完全夹断和紧凑体积中的低截止电流。

公开(公告)号：US08169007B2

公开(公告)日：2012-05-01

申请号：US13037485

申请日：2011-03-01

申请人： Frederick G. Anderson ,  David S. Collins ,  Richard A. Phelps ,  Robert M. Rassel ,  Michael J. Zierak

发明人： Frederick G. Anderson ,  David S. Collins ,  Richard A. Phelps ,  Robert M. Rassel ,  Michael J. Zierak

IPC分类号： H01L29/00 ,  H01L29/76

CPC分类号： H01L29/1058 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0843 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/20 ,  H01L29/22 ,  H01L29/66901 ,  H01L29/808

摘要： A junction field effect transistor (JFET) in a semiconductor substrate includes a source region, a drain region, a channel region, an upper gate region, and a lower gate region. The lower gate region is electrically connected to the upper gate region. The upper and lower gate regions control the current flow through the channel region. By performing an ion implantation step that extends the thickness of the source region to a depth greater than the thickness of the drain region, an asymmetric JFET is formed. The extension of depth of the source region relative to the depth of the drain region reduces the length for minority charge carriers to travel through the channel region, reduces the on-resistance of the JFET, and increases the on-current of the JFET, thereby enhancing the overall performance of the JFET without decreasing the allowable Vds or dramatically increasing Voff/Vpinch.

摘要翻译： 半导体衬底中的结型场效应晶体管（JFET）包括源极区，漏极区，沟道区，上部栅极区域和下部栅极区域。 下栅极区域电连接到上栅极区域。 上下栅极区域控制通过沟道区域的电流。 通过执行将源极区域的厚度延伸到大于漏极区域的厚度的深度的离子注入步骤，形成非对称JFET。 源极区域相对于漏极区域的深度的深度的扩展减小了少数电荷载流子穿过沟道区域的长度，减小了JFET的导通电阻，并增加了JFET的导通电流，由此 提高JFET的整体性能，而不会降低容许的Vds或显着增加Voff / Vpinch。

公开(公告)号：US07902606B2

公开(公告)日：2011-03-08

申请号：US11972811

申请日：2008-01-11

申请人： John B. Campi, Jr. ,  Richard A. Phelps ,  Robert M. Rassel ,  Michael J. Zierak

发明人： John B. Campi, Jr. ,  Richard A. Phelps ,  Robert M. Rassel ,  Michael J. Zierak

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7838 ,  H01L21/26586 ,  H01L29/0653 ,  H01L29/0688 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/66659

摘要： A metal-oxide-semiconductor field effect transistor (MOSFET) has a body layer that follows the contour of exposed surfaces of a semiconductor substrate and contains a bottom surface of a shallow trench and adjoined sidewalls. A bottom electrode layer vertically abuts the body layer and provides an electrical bias to the body layer. A top electrode and source and drain regions are formed on the body layer. The thickness of the body layer is selected to allow full depletion of the body layer by the top electrode and a bottom electrode layer. The portion of the body layer underneath the shallow trench extends the length of a channel to enable a high voltage operation. Further, the MOSFET provides a double gate configuration and a tight control of the channel to enable a complete pinch-off of the channel and a low off-current in a compact volume.

摘要翻译： 金属氧化物半导体场效应晶体管（MOSFET）具有跟随半导体衬底的暴露表面的轮廓的主体层，并且包含浅沟槽的底表面和相邻的侧壁。 底部电极层垂直邻接体层并向身体层提供电偏压。 顶部电极和源极和漏极区域形成在主体层上。 选择体层的厚度以允许顶层电极和底电极层完全耗尽体层。 浅沟槽下面的体层的部分延伸通道的长度以实现高电压操作。 此外，MOSFET提供双栅极配置和通道的严格控制，以实现通道的完全夹断和紧凑体积中的低截止电流。

公开(公告)号：US20080315266A1

公开(公告)日：2008-12-25

申请号：US11767627

申请日：2007-06-25

申请人： Ebenezer E. Eshun ,  Jeffrey B. Johnson ,  Richard A. Phelps ,  Robert M. Rassel ,  Michael J. Zierak

发明人： Ebenezer E. Eshun ,  Jeffrey B. Johnson ,  Richard A. Phelps ,  Robert M. Rassel ,  Michael J. Zierak

IPC分类号： H01L29/80 ,  H01L21/337

CPC分类号： H01L29/808 ,  H01L27/0617 ,  H01L27/098 ,  H01L29/36 ,  H01L29/66901

摘要： A junction field effect transistor (JFET) has a hyperabrupt junction layer that functions as a channel of a JFET. The hyperabrupt junction layer is formed by two dopant profiles of opposite types such that one dopant concentration profile has a peak concentration depth at a tail end of the other dopant profile. The voltage bias to the channel is provided by a body that is doped with the same type of dopants as the gate. This is in contrast with conventional JFETs that have a body that is doped with the opposite conductivity type as the gate. The body may be electrically decoupled from the substrate by another reverse bias junction formed either between the body and the substrate or between a buried conductor layer beneath the body and the substrate. The capability to form a thin hyperabrupt junction layer allows formation of a JFET in a semiconductor-on-insulator substrate.

摘要翻译： 结型场效应晶体管（JFET）具有作为JFET通道的超破裂结层。 超破裂结层由相反类型的两个掺杂剂分布形成，使得一个掺杂剂浓度分布在另一个掺杂剂分布的尾端处具有峰值浓度深度。 通道的电压偏置由掺杂有与栅极相同类型的掺杂剂的主体提供。 这与传统的JFET相反，JFET具有以与栅极相反的导电类型掺杂的主体。 主体可以通过形成在主体和衬底之间或者在主体和衬底之下的掩埋导体层之间形成的另一反向偏压接合部与衬底电耦合。 形成薄的超破裂结层的能力允许在绝缘体上半导体衬底中形成JFET。