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公开(公告)号：US5778236A
公开(公告)日：1998-07-07
申请号：US649787
申请日：1996-05-17
CPC分类号： G06F13/24
摘要： A multiprocessing computer system which includes an interrupt controller coupled to an expansion bus. The programmable interrupt controller has multiple storage locations at the same address for multiple CPUs. The CPUs are coupled to a host bus which in turn is coupled to the expansion bus by means of a bus bridge. An arbiter is coupled to the host bus for arbitrating bus mastership amongst the CPUs. CPU host owner identification for access to the storage locations is transferred across bus bridge to the programmable interrupt controller synchronized with the buffered address and data.
摘要翻译： 一种多处理计算机系统，其包括耦合到扩展总线的中断控制器。 可编程中断控制器在多个CPU的同一地址具有多个存储位置。 CPU耦合到主机总线，主机总线又通过总线桥耦合到扩展总线。 仲裁器耦合到主机总线，用于仲裁CPU之间的总线主控权。 用于访问存储位置的CPU主机所有者标识通过总线桥传输到与缓冲的地址和数据同步的可编程中断控制器。
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2.发明授权Multiprocessing system employing an adaptive interrupt mapping mechanism and method 失效多处理系统采用自适应中断映射机制和方法
公开(公告)号：US5721931A
公开(公告)日：1998-02-24
申请号：US408003
申请日：1995-03-21
IPC分类号： G06F15/16 , G06F9/46 , G06F13/24 , G06F15/177 , G06F13/00
CPC分类号： G06F13/24
摘要： A symmetrical multiprocessing system is provided that includes a central interrupt control unit. The central interrupt control unit is coupled to a plurality of processing units and to a plurality of interrupt sources. The interrupt sources include a plurality of peripheral devices coupled to a first peripheral bus, such as a PCI bus. The interrupt sources also include devices coupled to a second peripheral bus, such as an ISA bus. The central interrupt control unit is operative in two modes. In a first mode, referred to as a pass through mode, interrupts from ISA peripheral devices are provided through an interrupt controller, such as cascaded type 8259 interrupt controllers, to the central interrupt control unit. The central interrupt control unit then passes the interrupt directly to a master processing unit. PCI interrupts are provided through a PCI mapper to other available interrupt inputs of the interrupt controller. The pass through mode advantageously allows backwards compatibility of the system with traditional operating systems such as DOS. During the advanced operating mode, the central interrupt control unit causes the PCI mapper to be disabled. In the advanced mode, interrupts from both PCI devices and ISA devices are provided directly to the central interrupt control unit. Since the PCI mapper is disabled during the advanced mode, additional ISA peripheral devices may be supported within the system without contending with PCI interrupts.
摘要翻译： 提供了包括中央中断控制单元的对称多处理系统。 中央中断控制单元耦合到多个处理单元和多个中断源。 中断源包括耦合到诸如PCI总线的第一外围总线的多个外围设备。 中断源还包括耦合到第二外围总线的设备，例如ISA总线。 中央中断控制单元有两种模式。 在被称为通过模式的第一模式中，来自ISA外围设备的中断通过诸如级联型8259中断控制器的中断控制器提供给中央中断控制单元。 中央中断控制单元然后将中断直接传递到主处理单元。 PCI中断通过PCI映射器提供给中断控制器的其他可用中断输入。 通过模式有利地允许系统与诸如DOS的传统操作系统的向后兼容性。 在高级操作模式下，中央中断控制单元使PCI映射器被禁用。 在高级模式下，两个PCI设备和ISA设备的中断都直接提供给中央中央控制单元。 由于在高级模式下禁用了PCI映射器，所以系统中可能会支持额外的ISA外围设备，而不会与PCI中断相冲突。
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3.发明授权Apparatus and method for storing interrupt source information in an interrupt controller based upon interrupt priority 失效基于中断优先级将中断源信息存储在中断控制器中的装置和方法
公开(公告)号：US5905898A
公开(公告)日：1999-05-18
申请号：US605873
申请日：1996-02-23
申请人： Qadeer A. Qureshi , Dan S. Mudgett , James R. MacDonald , Douglas D. Gephardt , Rodney W. Schmidt
发明人： Qadeer A. Qureshi , Dan S. Mudgett , James R. MacDonald , Douglas D. Gephardt , Rodney W. Schmidt
摘要： A programmable interrupt controller is provided for use in computer systems including one or more CPUs. The programmable interrupt controller includes an interrupt request interface, a storage device, and at least one processor interface having an interrupt nesting buffer. An interrupt request identification code is assigned to each interrupt request and stored in the nesting buffer. The interrupt request identification codes used to reference the interrupt requests are stored in order of their priority. Each nesting buffer need have only a number of entries equal to the number of priority levels.
摘要翻译： 提供可编程中断控制器，用于包括一个或多个CPU的计算机系统。 可编程中断控制器包括中断请求接口，存储设备以及具有中断嵌套缓冲器的至少一个处理器接口。 中断请求识别码分配给每个中断请求并存储在嵌套缓冲区中。 用于引用中断请求的中断请求标识代码按其优先顺序存储。 每个嵌套缓冲区只需要等于优先级数量的条目数。
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公开(公告)号：US08214543B2
公开(公告)日：2012-07-03
申请号：US13218305
申请日：2011-08-25
IPC分类号： G06F3/00
摘要： Systems and methods for controlling the capabilities of an High Definition Audio (HDA) system, wherein the system determines whether an optional component such as a plug-in card is connected to the system and then configures itself in a baseline configuration if the optional component is not connected or configures itself in a different, alternative configuration if the optional component is connected. In one embodiment, a codec of the system includes a programmable processor configured to read configuration authorization information and also read configuration information from the optional component if it is connected to the system. The processor also controls the configuration of the HDA system and the operation of the codec based on the authorization and configuration information. The system can thereby provide different features and functionality using the same hardware.
摘要翻译： 用于控制高清晰度音频（HDA）系统的能力的系统和方法，其中系统确定诸如插件卡的可选组件是否连接到系统，然后如果可选组件是 如果可选组件连接，则不连接或将其自身配置为不同的替代配置。 在一个实施例中，系统的编解码器包括可编程处理器，其被配置为读取配置授权信息，并且如果连接到系统则从可选组件读取配置信息。 处理器还根据授权和配置信息控制HDA系统的配置和编解码器的操作。 因此，该系统可以使用相同的硬件来提供不同的特征和功能。
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5.发明授权System for effecting communications between a computing device and a plurality of peripheral devices 失效用于实现计算设备和多个外围设备之间的通信的系统
公开(公告)号：US5862375A
公开(公告)日：1999-01-19
申请号：US622574
申请日：1996-03-25
申请人： Douglas D. Gephardt
发明人： Douglas D. Gephardt
CPC分类号： G06F13/4221 , G06F12/0684 , G06F13/22 , G06F13/4226
摘要： A system for effecting communications between a computing device and a plurality of peripheral devices which comprises a bus controller for controlling the communications, a plurality of feedback generator circuits for providing operational status information, each of the plurality of peripheral devices having an associated one of the plurality of feedback generator circuits. The system further comprises a bus for conveying signals between the bus controller and the plurality of peripheral devices. In the preferred embodiment, each of the plurality of peripheral devices has a respective address and each of the plurality of feedback generator circuits contains the operational status information for its respective peripheral device. The bus controller interrogates the plurality of peripheral devices, each of which causes its respective feedback generator circuit to respond to such interrogation by communicating its respective operational status information to the bus controller when a respective of the peripheral devices indicates that such information is to be passed.
摘要翻译： 一种用于实现计算设备和多个外围设备之间的通信的系统，其包括用于控制通信的总线控制器，用于提供操作状态信息的多个反馈发生器电路，所述多个外围设备中的每一个具有相关联的一个 多个反馈发生器电路。 该系统还包括用于在总线控制器和多个外围设备之间传送信号的总线。 在优选实施例中，多个外围设备中的每一个具有相应的地址，并且多个反馈发生器电路中的每一个包含用于其各个外围设备的操作状态信息。 总线控制器询问多个外围设备，当各个外围设备指示这样的信息将被传递时，每个外围设备使每个外部设备使其各自的反馈发生器电路响应于这种询问，通过将其相应的操作状态信息传送到总线控制器 。
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6.发明授权
公开(公告)号：US5768584A
公开(公告)日：1998-06-16
申请号：US710047
申请日：1996-09-10
CPC分类号： G06F9/4401 , G06F12/0653
摘要： A non-volatile memory chip enable encoding method allows the storage of both boot code and user application software within a common memory array. The chip enable encoding method further allows a variable number of memory banks to be provided within the non-volatile memory array and allows the system to power-up and execute the boot code before the array configurations are selected by firmware. In one embodiment, a memory controller includes four chip enable output lines for selectively enabling a plurality of ROM banks. One of the ROM banks includes boot code that is executed by the system microprocessor during system boot. If the user requires a ROM array consisting of four ROM banks, a separate chip enable output line is connected to each ROM bank. If the user instead requires a ROM array consisting of, for example, eight ROM banks, an external decoder may be connected to the four chip enable output lines. In this configuration, each output line of the decoder is coupled to a respective bank enable input line of the ROM banks. In either configuration, the chip enable lines are driven in a mutually exclusive relationship during system boot to access the boot code (stored within one of the ROM banks). Subsequently, the encoding of the chip enable signals at the chip enable output lines of the memory controller is dependent upon configuration information stored in a configuration register.
摘要翻译： 非易失性存储器芯片使能编码方法允许在公共存储器阵列中存储引导代码和用户应用软件。 芯片使能编码方法还允许在非易失性存储器阵列内提供可变数量的存储体，并且在固件选择阵列配置之前允许系统上电并执行引导代码。 在一个实施例中，存储器控制器包括用于选择性地启用多个ROM组的四个芯片使能输出线。 其中一个ROM库包括在系统引导期间由系统微处理器执行的引导代码。 如果用户需要由四个ROM组组成的ROM阵列，则每个ROM组连接有单独的芯片使能输出线。 如果用户需要由例如八个ROM组组成的ROM阵列，则外部解码器可以连接到四个芯片使能输出线。 在该配置中，解码器的每个输出线耦合到ROM组的相应的bank使能输入线。 在任一配置中，芯片使能线在系统引导期间以相互排斥的关系被驱动以访问引导代码（存储在ROM库之一内）。 随后，存储器控制器的芯片使能输出线处的芯片使能信号的编码取决于存储在配置寄存器中的配置信息。
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7.发明授权Dockable computer system capable of electric and electromagnetic communication 失效可进行电力和电磁通信的可移动计算机系统
公开(公告)号：US5668977A
公开(公告)日：1997-09-16
申请号：US642188
申请日：1996-05-06
CPC分类号： G06F13/4081 , G06F1/1632
摘要： A dockable computer system includes a portable computer (notebook or laptop) and a docking station (base unit). The portable computer and docking station both include a communication system so that messages can be communicated when the docking station is in an undocked state preparatory to a docked state. The communication system is preferably an infrared communication system. A communication protocol is also provided for generating an advance notice signal to warn of an impending dock. The communication protocol includes a CONNECT message, a CONNECT DETECTED message, and a CONFIRM message. Preferably, the CONNECT message is sent at a non-standard AT/PC baud rate. The communication system allows the dockable computer system to advantageously generate an advance notice signal of an impending dock and to transfer parameters necessary for the employment of sophisticated protective measures which protect the active buses of the portable computer and docking station during a docking event. Preferably, the portable computer performs an interrupt subroutine in response to receiving the CONNECT message. The notice signal is generated as part of the interrupt subroutine.
摘要翻译： 可停放的计算机系统包括便携式计算机（笔记本或笔记本电脑）和对接站（基本单元）。 便携式计算机和对接站都包括通信系统，使得当对接站处于准备停靠状态的解除停靠状态时可以传送消息。 通信系统优选地是红外通信系统。 还提供通信协议用于产生提前通知信号以警告即将到来的码头。 通信协议包括CONNECT消息，CONNECT DETECTED消息和CONFIRM消息。 优选地，以非标准AT / PC波特率发送CONNECT消息。 通信系统允许可停靠的计算机系统有利地生成即将到来的码头的预告信号，并且传送在对接事件期间保护便携式计算机和对接站的有源总线的复杂保护措施所必需的参数。 优选地，便携式计算机响应于接收到CONNECT消息而执行中断子程序。 通知信号是作为中断子程序的一部分生成的。
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8.发明授权System for controlling communications among a computer processing unit and a plurality of peripheral devices 失效用于控制计算机处理单元和多个外围设备之间的通信的系统
公开(公告)号：US5313597A
公开(公告)日：1994-05-17
申请号：US097868
申请日：1993-07-27
申请人： Douglas D. Gephardt
发明人： Douglas D. Gephardt
CPC分类号： G06F13/4059
摘要： A system for controlling communications among a computer processing unit and a plurality of peripheral devices which are arrayed in operative connection with a plurality of external buses. The system comprises a bus control circuit for effecting operative routing of address information regarding a respective peripheral device from the computer processing unit to an appropriate external bus, the respective peripheral device being in operative connection with the appropriate external bus. The bus control circuit also effects operative routing of data information from the respective peripheral device to another of the plurality of peripheral devices or to the computer processing unit according to the address information. The system further comprises a plurality of buffers for establishing operative interfaces between the system and each of the plurality of external buses and an internal bus for facilitating communications among the plurality of buffers, the bus control circuit, and the computer processing unit. The bus control circuit enables operative interconnections to the internal bus by the plurality of buffers and the computer processing unit and includes an information storage unit for retaining stored routing information representing all operative interconnections which can operatively occur, the bus control circuit effecting such enabling according to the stored routing information.
摘要翻译： 一种用于控制计算机处理单元和多个外围设备之间的通信的系统，所述多个外围设备被排列成与多个外部总线操作连接。 该系统包括一个总线控制电路，用于对来自计算机处理单元的各个外围设备的地址信息进行有效的路由选择到适当的外部总线，相应的外围设备与适当的外部总线可操作地连接。 总线控制电路还根据地址信息实现数据信息从各个外围设备到多个外围设备中的另一个或计算机处理单元的操作路由。 该系统还包括多个缓冲器，用于建立系统与多个外部总线中的每一个之间的操作接口以及用于促进多个缓冲器，总线控制电路和计算机处理单元之间的通信的内部总线。 总线控制电路通过多个缓冲器和计算机处理单元实现与内部总线的操作互连，并且包括用于保存表示可操作地发生的所有可操作互连的存储的路由信息的信息存储单元，总线控制电路根据 存储的路由信息。
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9.发明授权Apparatus for use with a computing device controlling communications with a plurality of peripheral devices including a feedback bus to indicate operational modes 失效用于与计算设备一起使用的设备，其控制与包括反馈总线的多个外围设备的通信以指示操作模式
公开(公告)号：US5175820A
公开(公告)日：1992-12-29
申请号：US800862
申请日：1991-10-25
申请人： Douglas D. Gephardt
发明人： Douglas D. Gephardt
CPC分类号： G06F13/4226 , G06F13/22
摘要： An apparatus for use with a computing device for controlling communications with a plurality of peripheral devices, each of which peripheral devices is operatively connected with a bus and is identified by an address. The apparatus comprises a control circuit for transmitting address information to the bus to effect interrogation of the plurality of peripheral devices, respective of the pluraity of peripheral devices being responding, or ready, peripheral devices according to address information transmitted by the control circuit. A plurality of modal circuits are provided for establishing a plurality of operational modes for the apparatus, as well as a decision circuit for effecting designation of selected of the plurality of modal circuits. The responding peripheral device transmits a status code to the bus in response to appropriate address information received from the control circuit, which status code includes at least a first indicator identifying an appropriate operational mode for communication with the responding peripheral device. The decision circuit is responsive to the first indicator to effect the required designation to establish which of the plurality of modal circuits will be employed to establish the appropriate operational mode for the responding peripheral device.
摘要翻译： 一种用于与计算设备一起使用的装置，用于控制与多个外围设备的通信，每个外围设备中的每一个外围设备与总线可操作地连接并由地址识别。 该装置包括控制电路，用于根据由控制电路发送的地址信息，向总线发送地址信息以实现多个外围设备的询问，外围设备的响应或准备好的周边设备的相应。 提供了多个模态电路，用于建立用于装置的多个操作模式，以及用于实现所选择的多个模态电路的指定的判定电路。 响应的外围设备响应于从控制电路接收到的适当地址信息向总线发送状态码，该状态代码至少包括标识用于与响应的外围设备进行通信的适当操作模式的第一指示符。 决定电路响应于第一指示符来实现所需的指定，以建立多个模态电路中的哪一个将用于为响应的外围设备建立适当的操作模式。
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10.发明授权Streaming multi-channel audio as packetized data or parallel data with a separate input frame sync 失效将多通道音频流作为分组数据或具有单独输入帧同步的并行数据公开(公告)号：US07738613B1
公开(公告)日：2010-06-15
申请号：US10805574
申请日：2004-03-20
IPC分类号： H04L7/00
CPC分类号： H04L7/0029 , H03H17/0275 , H03H17/0685 , H04L7/005 , H04L25/4902
摘要： Systems and methods for converting a data stream from a first sample rate to a second sample rate, where the data is received in bursts. In one embodiment, a method includes receiving bursty audio data on a first input line and receiving synchronization data on a second input line that is separate from the first input line. An input sample rate is then estimated for the received audio data based on the received synchronization data and the audio data is converted to an output sample rate. The input sample rate is determined by counting samples received in a time interval and potentially low-pass filtering the result. The audio data may be in packetized, parallel, or other forms, and the synchronization data may include individual signals, such as pulses or bits received at regular or irregular intervals.
摘要翻译： 用于将数据流从第一采样率转换为第二采样率的系统和方法，其中数据以突发方式接收。 在一个实施例中，一种方法包括在第一输入线上接收突发音频数据，并在与第一输入线分开的第二输入线上接收同步数据。 然后，基于接收到的同步数据对接收到的音频数据估计输入采样率，并将音频数据转换为输出采样率。 输入采样率通过对在时间间隔中接收到的样本进行计数并潜在地对结果进行低通滤波来确定。 音频数据可以是打包的，并行的或其他形式，并且同步数据可以包括各种信号，例如以规则或不规则的间隔接收的脉冲或位。
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