公开(公告)号：US06516422B1

公开(公告)日：2003-02-04

申请号：US09320794

申请日：1999-05-27

申请人： Drew G. Doblar ,  Leo Yuan ,  Emrys J. Williams

发明人： Drew G. Doblar ,  Leo Yuan ,  Emrys J. Williams

IPC分类号： G06F1100

CPC分类号： G06F11/1604 ,  G06F1/04 ,  G06F11/20

摘要： A system and method for providing redundant, synchronized clocks in a computer system. Upon a failure of a master clock signal, the system switches over to a slave clock signal synchronized with the master clock signal. Switching logic is coupled to receive a first clock signal and a second clock signal. The switching logic selects either the first clock signal or the second clock signal as a local clock signal. The switching logic further monitors the first clock signal for a failure. If a failure is monitored, the switching logic accepts the second clock signal as the local clock signal in place of the first clock signal. One or more clock local loads operate according to the local clock signal. The switching logic may control the input to a phase locked loop (PLL) that provides the local clock signal to the local clock loads. The method includes a PLL synchronizing an output clock signal with the master clock signal. The output clock signal is used by at least one local clock load for timing. The switching logic monitors the master clock signal and the slave clock signal for a failure. Upon a failure of either the master clock signal or the slave clock signal, the switching logic notifies a system controller of the failure. Upon the failure of the first clock signal, the switching logic switches the second clock signal in place of the first clock signal as the master clock signal for the PLL, causes the second clock signal to fail-over and to take over as the master clock source to the PLL, and causes the second clock source to provide a reference control signal to the second clock source. Clock switching is automatic and does not interrupt or interfere with operation of the computer system.

摘要翻译： 一种用于在计算机系统中提供冗余的同步时钟的系统和方法。 在主时钟信号故障时，系统切换到与主时钟信号同步的从时钟信号。 开关逻辑被耦合以接收第一时钟信号和第二时钟信号。 开关逻辑选择第一时钟信号或第二时钟信号作为本地时钟信号。 开关逻辑进一步监视第一时钟信号以进行故障。 如果监视故障，则开关逻辑代替第一个时钟信号接收第二个时钟信号作为本地时钟信号。 一个或多个时钟本地负载根据本地时钟信号工作。 开关逻辑可以将输入控制到将本地时钟信号提供给本地时钟负载的锁相环（PLL）。 该方法包括使输出时钟信号与主时钟信号同步的PLL。 输出时钟信号由至少一个本地时钟负载用于定时。 开关逻辑监视主时钟信号和从时钟信号以进行故障。 在主时钟信号或从时钟信号失效时，开关逻辑通知系统控制器故障。 当第一时钟信号失效时，开关逻辑将第二时钟信号替换为第一时钟信号，作为PLL的主时钟信号，使第二时钟信号故障切换并接管作为主时钟 源，并使第二时钟源向第二时钟源提供参考控制信号。 时钟切换是自动的，不会中断或干扰计算机系统的操作。

公开(公告)号：US06477205B1

公开(公告)日：2002-11-05

申请号：US09324399

申请日：1999-06-03

申请人： Drew G. Doblar ,  Leo Yuan

发明人： Drew G. Doblar ,  Leo Yuan

IPC分类号： H04L2700

CPC分类号： H04L25/0278 ,  H04L25/0272 ,  H04L25/028 ,  H04L25/0292 ,  H04L25/4904 ,  H04L25/4923

摘要： A digital communication system is presented including at least one transmission line coupled between a first and second communication devices and used to convey binary data from the first communication device to the second communication device. A termination resistor and one end of the transmission line are coupled to an input node of the second communication device. An electrical voltage level existing at the input node of the second communication device may be substantially dependent upon an amount of electrical current flowing through the termination resistor. The termination resistor may have a value substantially equal to a characteristic impedance of the transmission line such that signal reflections and distortion occurring within the transmission line are substantially reduced. Three or more different voltage levels may be present upon the transmission line dependent upon the binary data. The resulting increase in data transmission capability may be used to reduce the total number of transmission lines coupled between the first and second communication devices, or to increase the rate at which the binary data is transmitted from the first communication device to the second communication device. The ternary signals may also be used to encode a clock signal with binary data upon one or more transmission lines such that a separate clock transmission line is not needed, and clock signal reception is ensured even in case of transmission line failure.

摘要翻译： 提供了一种数字通信系统，其包括耦合在第一和第二通信设备之间的至少一个传输线，并用于将二进制数据从第一通信设备传送到第二通信设备。 终端电阻器和传输线路的一端耦合到第二通信设备的输入节点。 存在于第二通信设备的输入节点处的电压电平可以基本上取决于流过终端电阻器的电流量。 终端电阻器可以具有基本上等于传输线的特性阻抗的值，使得在传输线内发生的信号反射和失真显着减小。 取决于二进制数据，传输线上可能存在三个或更多个不同的电压电平。 所导致的数据传输能力的增加可以用于减少耦合在第一和第二通信设备之间的传输线的总数，或者增加二进制数据从第一通信设备发送到第二通信设备的速率。 三进制信号也可以用于在一条或多条传输线上对具有二进制数据的时钟信号进行编码，使得不需要单独的时钟传输线，并且即使在传输线路故障的情况下也能确保时钟信号的接收。

公开(公告)号：US20060009931A1

公开(公告)日：2006-01-12

申请号：US11224277

申请日：2005-09-12

申请人： Brian Smith ,  Jue Wu ,  Jyh-Ming Jong ,  Wai Fong ,  Leo Yuan ,  Prabhansu Chakrabarti

发明人： Brian Smith ,  Jue Wu ,  Jyh-Ming Jong ,  Wai Fong ,  Leo Yuan ,  Prabhansu Chakrabarti

IPC分类号： G01R31/00

CPC分类号： G06F11/24 ,  H02H1/00 ,  H02H3/385 ,  H02H7/267

摘要： A method and apparatus for automated calibration of I/O over a multi-variable eye window is provided. A transmitter may conduct data transmissions to a receiver of an integrated circuit (IC) over a plurality of signal lines. The data transmissions may be conducted according to a certain parameters or sets of parameters. Parameters may include voltage levels at which signals are transmitted or timing delays. The receiver may determine whether the correct data value was received over each signal line. The results may be recorded in a storage mechanism in the same IC as the receiver. The storage mechanism may, for each signal line, store a pass/fail result corresponding to the particular parameters for the data transmission. The system may select the parameters which subsequent transmissions are to be conducted over each of the plurality of signal lines from the storage mechanism.

公开(公告)号：US07130340B1

公开(公告)日：2006-10-31

申请号：US09698622

申请日：2000-10-27

申请人： Jyh-Ming Jong ,  Leo Yuan

发明人： Jyh-Ming Jong ,  Leo Yuan

IPC分类号： H04B3/46

CPC分类号： H04B3/46 ,  H04L25/08

摘要： A noise margin self-diagnostic receiver circuit has been developed. The self-diagnostic circuit includes one comparator for comparing the signal voltage to a high reference voltage, a second comparator for comparing the signal voltage to a low reference voltage, and a logic circuit that activates an alarm if a noise error is detected. The circuit analyzes the data from the comparators and determines if a noise error has occurred dependent on being clocked by one or both of an output from the comparator comparing the signal voltage to the high reference voltage and an output from the comparator comparing the signal voltage to the low reference voltage.

摘要翻译： 已经开发了噪声容限自诊断接收机电路。 自诊断电路包括用于将信号电压与高参考电压进行比较的一个比较器，用于将信号电压与低参考电压进行比较的第二比较器以及如果检测到噪声误差则激活报警的逻辑电路。 电路分析来自比较器的数据，并且确定是否发生了噪声误差，这取决于由比较器中的一个或两个比较信号电压与高参考电压的时钟，以及来自比较器的输出比较信号电压与 低参考电压。

公开(公告)号：US4597029A

公开(公告)日：1986-06-24

申请号：US591342

申请日：1984-03-19

申请人： Andrzej Kucharek ,  John Marshall ,  James C. K. Lee ,  Carlton G. Amdahl ,  Leo Yuan

发明人： Andrzej Kucharek ,  John Marshall ,  James C. K. Lee ,  Carlton G. Amdahl ,  Leo Yuan

IPC分类号： H05K7/10 ,  H01R9/00

CPC分类号： H05K7/1053

摘要： A semiconductor chip having a two-dimensional array of contacts on an exposed face thereof is mounted in a semiconductor chip module. A mechanism for delivering electricity spans the exposed face of the chip to which it is connected and includes interstitial gaps. A conductor board has a surface proximate the electricity delivering mechanism opposite from the chip. The surface of the board has a two-dimensional array of contacts which correspond to at least some of the contacts on the chip. A biasing mechanism extends from the electricity delivering mechanism toward the exposed face of the semiconductor chip and toward the conductor board, and corresponds to the array of contacts on the chip and board. Signal leads pass through the interstitial gaps and have end portions which extend transversely over the biasing means. The end portions of the signal leads are biased against the contacts of the chips and board by the biasing mechanism.

摘要翻译： 在半导体芯片模块中安装有在其暴露表面上具有二维接触阵列的半导体芯片。 用于传递电力的机构跨越与其连接的芯片的暴露面并且包括间隙。 导体板具有与芯片相对的电力输送机构的表面。 板的表面具有对应于芯片上的至少一些触点的触点的二维阵列。 偏置机构从电力输送机构朝向半导体芯片的露出面朝向导体板延伸，并且对应于芯片和板上的触点阵列。 信号引线通过间隙隙并且具有在偏置装置上横向延伸的端部。 信号引线的端部通过偏置机构偏置在芯片和板的触点上。

公开(公告)号：US06944692B2

公开(公告)日：2005-09-13

申请号：US09951928

申请日：2001-09-13

申请人： Brian L. Smith ,  Jue Wu ,  Jyh-Ming Jong ,  Wai Fong ,  Leo Yuan ,  Prabhansu Chakrabarti

发明人： Brian L. Smith ,  Jue Wu ,  Jyh-Ming Jong ,  Wai Fong ,  Leo Yuan ,  Prabhansu Chakrabarti

IPC分类号： H04L25/02 ,  G06F1/10 ,  G06F11/24 ,  G06F13/00 ,  G06F13/42 ,  G06K5/04 ,  H02H1/00 ,  H02H3/38 ,  H02H7/26 ,  H04L25/03 ,  G06F11/04

CPC分类号： G06F11/24 ,  H02H1/00 ,  H02H3/385 ,  H02H7/267

摘要： A method and apparatus for automated calibration of I/O over a multi-variable eye window is provided. A transmitter may conduct data transmissions to a receiver of an integrated circuit (IC) over a plurality of signal lines. The data transmissions may be conducted according to a certain parameters or sets of parameters. Parameters may include voltage levels at which signals are transmitted or timing delays. The receiver may determine whether the correct data value was received over each signal line. The results may be recorded in a storage mechanism in the same IC as the receiver. The storage mechanism may, for each signal line, store a pass/fail result corresponding to the particular parameters for the data transmission. The system may select the parameters which subsequent transmissions are to be conducted over each of the plurality of signal lines from the storage mechanism.

摘要翻译： 提供了一种用于通过多变量眼窗自动校准I / O的方法和装置。 发射机可以通过多条信号线对集成电路（IC）的接收机进行数据传输。 可以根据某些参数或参数集进行数据传输。 参数可以包括传输信号的电压电平或定时延迟。 接收机可以确定是否在每个信号线上接收到正确的数据值。 结果可以记录在与接收器相同的IC中的存储机构中。 对于每个信号线，存储机构可以存储对应于用于数据传输的特定参数的通过/失败结果。 系统可以从存储机构中选择要在多条信号线中的每条信号上进行后续传输的参数。

公开(公告)号：US06937680B2

公开(公告)日：2005-08-30

申请号：US09842332

申请日：2001-04-24

申请人： Wai Fong ,  Jyh-Ming Jong ,  Leo Yuan ,  Brian Smith ,  Prabhansu Chakrabarti

发明人： Wai Fong ,  Jyh-Ming Jong ,  Leo Yuan ,  Brian Smith ,  Prabhansu Chakrabarti

IPC分类号： G06F1/12 ,  H03L7/081 ,  H03L7/095 ,  H04L7/00

CPC分类号： H03L7/0812 ,  H03L7/095 ,  H04L7/0008

摘要： A method and apparatus for operating a source synchronous receiver. In one embodiment, a source synchronous receiver may include a clock receiver comprising a clock detector and a clock signal buffer. The clock detector may be configured to detect a first clock signal and assert a clock detect signal responsive to detecting the first clock signal. The clock buffer may receive the first clock signal and produce a second clock signal, which may be driven to a digital locked loop (DLL) circuit, where the second clock signal is regenerated and driven to a data buffer of the source synchronous receiver. The clock detect signal may be received by a clock verification circuit. The clock verification circuit may be configured to initiate a reset of the source synchronous receiver upon a failure to receive the clock detect signal. The resetting of the source synchronous receiver may be performed locally, and does not reset the core logic of the device in which it is implemented, nor any other source synchronous port on the device. Thus, other source synchronous ports on the device, as well as the core logic, may be able to continue operations as normal. The method and apparatus may include a source synchronous receiver that is hot-swappable.

摘要翻译： 一种用于操作源同步接收机的方法和装置。 在一个实施例中，源同步接收器可以包括包括时钟检测器和时钟信号缓冲器的时钟接收器。 时钟检测器可以被配置为响应于检测到第一时钟信号而检测第一时钟信号并且断言时钟检测信号。 时钟缓冲器可以接收第一时钟信号并产生可以被驱动到数字锁相环（DLL）电路的第二时钟信号，其中第二时钟信号被再生并被驱动到源同步接收器的数据缓冲器。 时钟检测信号可以由时钟验证电路接收。 时钟验证电路可以被配置为在接收到时钟检测信号的失败时发起源同步接收器的复位。 源同步接收机的复位可以在本地执行，并且不重置其实现的设备的核心逻辑，也不会重置设备上的任何其他源同步端口。 因此，设备上的其他源同步端口以及核心逻辑可能能够正常地继续操作。 该方法和装置可以包括热插拔的源同步接收器。

公开(公告)号：US06518792B2

公开(公告)日：2003-02-11

申请号：US09879501

申请日：2001-06-11

申请人： Jyh-Ming Jong ,  Prabhansu Chakrabarti ,  Leo Yuan

发明人： Jyh-Ming Jong ,  Prabhansu Chakrabarti ,  Leo Yuan

IPC分类号： H03K190175

CPC分类号： H04L25/0286 ,  H04L25/0272

摘要： A method and circuitry for pre-emphasizing transmitted logic signals. The method and circuitry may be applied to single-ended center-taped terminated I/O lines. In one embodiment, a driver circuit may be configured for monitoring the logic values (i.e. logic 0, logic 1, or logic low, logic high) of signals transmitted by the driver circuit. The driver circuit may compare the logic value of a next logic signal to be transmitted with a first previously transmitted signal and a second previously transmitted signal. Pre-emphasis of the next logic signal may occur based on the logic value of the next logic signal to be transmitted as well as the logic values of the first and second logic signals. If the first and second logic signals have the same logic value, and the next logic signal has a different value, the next logic value may be pre-emphasized. If the next logic signal has a logic value that is equivalent to either the first logic signal or the second logic signal, it may be transmitted without pre-emphasis.

摘要翻译： 一种预先强调传输逻辑信号的方法和电路。 该方法和电路可以应用于单端中心点终端I / O线。 在一个实施例中，驱动器电路可以被配置为监视由驱动器电路发送的信号的逻辑值（即逻辑0，逻辑1或逻辑低，逻辑高）。 驱动器电路可以将要发送的下一逻辑信号的逻辑值与先前发送的第一信号和第二先前发送的信号进行比较。 基于要发送的下一逻辑信号的逻辑值以及第一和第二逻辑信号的逻辑值，可能发生下一个逻辑信号的预加重。 如果第一和第二逻辑信号具有相同的逻辑值，并且下一逻辑信号具有不同的值，则可以预先强调下一个逻辑值。 如果下一个逻辑信号具有等同于第一逻辑信号或第二逻辑信号的逻辑值，则可以在没有预加重的情况下发送它。

公开(公告)号：US4553050A

公开(公告)日：1985-11-12

申请号：US565318

申请日：1983-12-27

申请人： Irving Feinberg ,  Leon L. Wu ,  Leo Yuan

发明人： Irving Feinberg ,  Leon L. Wu ,  Leo Yuan

IPC分类号： H01L21/822 ,  H01L21/8222 ,  H01L23/522 ,  H01L27/04 ,  H01L27/06 ,  H01L27/07 ,  H03K19/003 ,  H03H5/02 ,  H03H7/38

CPC分类号： H03K19/00346 ,  H01L23/5223 ,  H01L27/0794 ,  H01L2924/0002

摘要： A signal transmission line terminator for an off-chip driver circuit is disclosed in which each capacitor and resistor comprising each terminator are formed on the same chip separate from the driver circuit chip. The close proximity of the elements of the terminator reduce the path lengths therebetween to a minimum. The structure substantially eliminates the corresponding inductive reactance and concommitant .DELTA.I noise at high switching rates employed in high performance computers.

摘要翻译： 公开了一种用于片外驱动电路的信号传输线路终端器，其中包括每个终端器的每个电容器和电阻器形成在与驱动器电路芯片分离的同一芯片上。 终端器的元件的紧密接近使其间的路径长度最小化。 该结构基本上消除了在高性能计算机中使用的高开关率下的相应的电抗和伴随的DELTA I噪声。

公开(公告)号：US07296104B2

公开(公告)日：2007-11-13

申请号：US11224277

申请日：2005-09-12

申请人： Brian L. Smith ,  Jue Wu ,  Jyh-Ming Jong ,  Wai Fong ,  Leo Yuan ,  Prabhansu Chakrabarti

发明人： Brian L. Smith ,  Jue Wu ,  Jyh-Ming Jong ,  Wai Fong ,  Leo Yuan ,  Prabhansu Chakrabarti

IPC分类号： G06F13/42 ,  G06F11/04 ,  G06K5/04

CPC分类号： G06F11/24 ,  H02H1/00 ,  H02H3/385 ,  H02H7/267

摘要： A method and apparatus for automated calibration of I/O over a multi-variable eye window is provided. A transmitter may conduct data transmissions to a receiver of an integrated circuit (IC) over a plurality of signal lines. The data transmissions may be conducted according to a certain parameters or sets of parameters. Parameters may include voltage levels at which signals are transmitted or timing delays. The receiver may determine whether the correct data value was received over each signal line. The results may be recorded in a storage mechanism in the same IC as the receiver. The storage mechanism may, for each signal line, store a pass/fail result corresponding to the particular parameters for the data transmission. The system may select the parameters which subsequent transmissions are to be conducted over each of the plurality of signal lines from the storage mechanism.

摘要翻译： 提供了一种用于通过多变量眼窗自动校准I / O的方法和装置。 发射机可以通过多条信号线对集成电路（IC）的接收机进行数据传输。 可以根据某些参数或参数集进行数据传输。 参数可以包括传输信号的电压电平或定时延迟。 接收机可以确定是否在每个信号线上接收到正确的数据值。 结果可以记录在与接收器相同的IC中的存储机构中。 对于每个信号线，存储机构可以存储对应于用于数据传输的特定参数的通过/失败结果。 系统可以从存储机构中选择要在多条信号线中的每条信号上进行后续传输的参数。