公开(公告)号：US6026465A

公开(公告)日：2000-02-15

申请号：US897499

申请日：1997-06-18

申请人： Duane R. Mills ,  Brian Lyn Dipert ,  Sachidanandan Sambandan ,  Bruce McCormick ,  Richard D. Pashley

发明人： Duane R. Mills ,  Brian Lyn Dipert ,  Sachidanandan Sambandan ,  Bruce McCormick ,  Richard D. Pashley

IPC分类号： G06F12/06 ,  G06F12/08 ,  G11C7/10 ,  G06F13/16 ,  G06F12/00

CPC分类号： G06F12/08 ,  G06F12/0607 ,  G11C7/1045 ,  G11C7/1072 ,  G06F2212/2022 ,  Y02B60/1225

摘要： A flash memory chip that can be switched into four different read modes is described. In the first read mode, asynchronous flash mode, the flash memory is read as a standard flash memory where the reading of the contents of a first address must be completed before a second address to be read can be specified. In the second read mode, synchronous flash mode, a clock signal is provided to the flash chip and a series of addresses belonging to a data burst are specified, one address per clock tick. Then, the contents stored at the addresses specified for the burst are output sequentially during subsequent clock ticks in the order in which the addresses were provided. Alternately, if a single address is provided to the flash chip when it is in the synchronous mode, the subsequent addresses for the burst will be generated within the flash chip and the data burst will then be provided as output from the flash chip. In the third read mode, asynchronous DRAM mode, the row and column addresses are strobed into the flash memory using strobe signals. The flash memory then converts the row and column addresses internally into a single address and provides as output the data stored at that single address. The flash memory does not need an extended precharge period or to be refreshed, but can be controlled by a standard DRAM controller. In the fourth read mode, synchronous DRAM mode, the flash memory emulates a synchronous DRAM.

摘要翻译： 描述可以切换成四种不同读取模式的闪存芯片。 在第一读取模式，异步闪存模式下，闪存被读取为标准闪速存储器，其中在可以指定要读取的第二地址之前必须先完成读取第一地址的内容。 在第二读取模式的同步闪光模式中，向闪存芯片提供时钟信号，并且指定属于数据突发的一系列地址，每个时钟刻度一个地址。 然后，按照提供地址的顺序，在随后的时钟周期期间顺序输出存储在针对脉冲串指定的地址的内容。 或者，如果在闪存芯片处于同步模式时提供单个地址，则在闪存芯片内将生成用于突发的后续地址，然后将数据突发作为闪存芯片的输出提供。 在第三读取模式下，异步DRAM模式，使用选通信号将行和列地址选通闪存。 然后，闪存将内部的行和列地址转换为单个地址，并提供存储在该单个地址的数据的输出。 闪存不需要扩展预充电周期或刷新，而是可以由标准DRAM控制器控制。 在第四读取模式，同步DRAM模式下，闪速存储器模拟同步DRAM。

公开(公告)号：US5696917A

公开(公告)日：1997-12-09

申请号：US253499

申请日：1994-06-03

申请人： Duane R. Mills ,  Brian Lyn Dipert ,  Sachidanandan Sambandan ,  Bruce McCormick ,  Richard D. Pashley

发明人： Duane R. Mills ,  Brian Lyn Dipert ,  Sachidanandan Sambandan ,  Bruce McCormick ,  Richard D. Pashley

IPC分类号： G06F12/06 ,  G06F12/08 ,  G11C7/10 ,  G06F12/00

CPC分类号： G06F12/08 ,  G06F12/0607 ,  G11C7/1045 ,  G11C7/1072 ,  G06F2212/2022 ,  Y02B60/1225

摘要： An asynchronous nonvolatile memory includes a plurality of individual memory components. A burst read operation references consecutive addresses beginning with a first address, wherein the consecutive addresses are not located in a same memory component. A method of performing a burst read operation in the asynchronous nonvolatile memory includes the step of providing the first address as a current address to the plurality of individual components. A current page identified by m higher order bits of the current address is selected. Each of the individual memory components senses a location identified by the m higher order bits. An output of a selected individual memory component is enabled in accordance with n lower bits of the current address. A consecutive subsequent address is provided, wherein the current address becomes a preceding address and the consecutive subsequent address becomes the current address. The output of another selected individual memory component identified by the n lower order bits of the current address is enabled without generating wait states, if the current and preceding addresses identify a same page. The process of providing consecutive subsequent addresses and enabling the output of a memory component identified by the n lower order bits is repeated as long as the current and preceding addresses identify the same page.

摘要翻译： 异步非易失性存储器包括多个单独的存储器组件。 突发读取操作参考以第一地址开头的连续地址，其中连续地址不位于相同的存储器组件中。 在异步非易失性存储器中执行突发读取操作的方法包括将第一地址作为当前地址提供给多个单独的组件的步骤。 选择当前地址的m个更高阶位所标识的当前页。 每个单独的存储器组件感测由m个更高阶位确定的位置。 根据当前地址的n个较低位使能所选择的各个存储器组件的输出。 提供连续的后续地址，其中当前地址变为前一地址，并且连续的后续地址变为当前地址。 如果当前地址和以前的地址标识同一页，则由当前地址的n个较低位确定的另一个选定的单独存储器组件的输出被启用而不产生等待状态。 只要当前和前面的地址标识相同的页面，就重复提供连续的后续地址并且使得能够输出由n个较低位比特识别的存储器组件的处理。

公开(公告)号：US06564285B1

公开(公告)日：2003-05-13

申请号：US09595327

申请日：2000-06-14

申请人： Duane R. Mills ,  Brian Lyn Dipert ,  Sachidanandan Sambandan ,  Bruce McCormick ,  Richard D. Pashley

发明人： Duane R. Mills ,  Brian Lyn Dipert ,  Sachidanandan Sambandan ,  Bruce McCormick ,  Richard D. Pashley

IPC分类号： G06F1200

CPC分类号： G06F12/08 ,  G06F12/0607 ,  G06F2212/2022 ,  G11C7/1045 ,  G11C7/1072 ,  Y02D10/13

摘要： A flash memory chip that can be switched into four different read modes is described. In asynchronous flash mode, the flash memory is read as a standard flash memory. In synchronous flash mode, a clock signal is provided to the flash chip and a series of addresses belonging to a data burst are specified, one address per clock period. The data stored at the specified addresses are output sequentially during subsequent clock periods. In asynchronous DRAM mode, the flash memory emulates DRAM. In synchronous DRAM mode the flash memory emulates synchronous DRAM.

摘要翻译： 描述可以切换成四种不同读取模式的闪存芯片。 在异步闪存模式下，闪存作为标准闪存读取。 在同步闪光模式中，向闪存芯片提供时钟信号，并且指定属于数据脉冲串的一系列地址，每个时钟周期一个地址。 存储在指定地址处的数据在后续时钟周期内顺序输出。 在异步DRAM模式下，闪存模拟DRAM。 在同步DRAM模式下，闪存模拟同步DRAM。

公开(公告)号：US06385688B1

公开(公告)日：2002-05-07

申请号：US08877840

申请日：1997-06-18

申请人： Duane R. Mills ,  Brian Lyn Dipert ,  Sachidanandan Sambandan ,  Bruce McCormick ,  Richard D. Pashley

发明人： Duane R. Mills ,  Brian Lyn Dipert ,  Sachidanandan Sambandan ,  Bruce McCormick ,  Richard D. Pashley

IPC分类号： G06F1200

CPC分类号： G06F12/08 ,  G06F12/0607 ,  G06F2212/2022 ,  G11C7/1045 ,  G11C7/1072 ,  Y02D10/13

摘要： A flash memory chip that can be switched into four different read modes is described. In asynchronous flash mode, the flash memory is read as a standard flash memory. In synchronous flash mode, a clock signal is provided to the flash chip and a series of addresses belonging to a data burst are specified, one address per clock period. The data stored at the specified addresses are output sequentially during subsequent clock periods. In asynchronous DRAM mode, the flash memory emulates DRAM. In synchronous DRAM mode, the flash memory emulates synchronous DRAM.

摘要翻译： 描述可以切换成四种不同读取模式的闪存芯片。 在异步闪存模式下，闪存作为标准闪存读取。 在同步闪光模式中，向闪存芯片提供时钟信号，并且指定属于数据脉冲串的一系列地址，每个时钟周期一个地址。 存储在指定地址处的数据在后续时钟周期内顺序输出。 在异步DRAM模式下，闪存模拟DRAM。 在同步DRAM模式下，闪存模拟同步DRAM。

公开(公告)号：US5978833A

公开(公告)日：1999-11-02

申请号：US777253

申请日：1996-12-31

申请人： Richard D. Pashley ,  Bruce McCormick

发明人： Richard D. Pashley ,  Bruce McCormick

IPC分类号： G06F17/30

CPC分类号： G06F17/30899

摘要： A method and apparatus for accessing and downloading information from the internet to a hand held computer system. The computer system includes a bus to which a processor, a display screen, input keys, and a flash memory are coupled. The flash memory stores an operating system for the computer system, search criteria, information corresponding to the search criteria downloaded from the internet, and display application software for displaying the information on the display screen.

摘要翻译： 一种用于从互联网访问和下载信息到手持计算机系统的方法和装置。 计算机系统包括一个总线，处理器，显示屏，输入键和闪速存储器耦合到该总线。 闪存存储用于计算机系统的操作系统，搜索标准，与从因特网下载的搜索条件相对应的信息，以及用于在显示屏幕上显示信息的显示应用软件。

公开(公告)号：USRE44877E1

公开(公告)日：2014-04-29

申请号：US10770959

申请日：2004-02-02

申请人： Richard D. Pashley ,  Bruce McCormick

发明人： Richard D. Pashley ,  Bruce McCormick

IPC分类号： G06F15/16

摘要： A method and apparatus for accessing and downloading information from the internet to a hand held computer system. The computer system includes a bus to which a processor, a display screen, input keys, and a flash memory are coupled. The flash memory stores an operating system for the computer system, search criteria, information corresponding to the search criteria downloaded from the internet, and display application software for displaying the information on the display screen.

摘要翻译： 一种用于从互联网访问和下载信息到手持计算机系统的方法和装置。 计算机系统包括一个总线，处理器，显示屏，输入键和闪速存储器耦合到该总线。 闪存存储用于计算机系统的操作系统，搜索标准，与从因特网下载的搜索条件相对应的信息，以及用于在显示屏幕上显示信息的显示应用软件。

公开(公告)号：US20120318808A1

公开(公告)日：2012-12-20

申请号：US13333386

申请日：2011-12-21

申请人： Bruce McCormick

发明人： Bruce McCormick

IPC分类号： B65D81/38

CPC分类号： F16L59/065 ,  B65D81/18 ,  B65D81/2076

摘要： A storage container that includes walls having complimentary-shaped edges with complex edge profiles. The complex edge profiles of adjoining walls mate with each other to form an interface that defines a thermal leak path between a storage area of the container and an exterior environment. The thermal leak path has a length that is greater than the thickness of the adjoined walls. In one example, the complex edge profile includes step-shaped features. The walls may also include one or more overlapping super-insulating panels. The panels may be joined to one another with adhesive layers. The super-insulating panels may be also be disposed in a wall including interior and exterior linings that are joined and sealed to define a space between the linings. The space may be evacuated and optionally filled with a super-insulating gas.

摘要翻译： 一种储存容器，其包括具有互补形状边缘且具有复杂边缘轮廓的壁。 相邻壁的复杂边缘轮廓彼此配合以形成限定容器的存储区域和外部环境之间的热泄漏路径的界面。 热泄漏路径的长度大于相邻壁的厚度。 在一个示例中，复杂边缘轮廓包括阶梯形特征。 墙壁还可以包括一个或多个重叠的超绝缘面板。 面板可以用粘合剂层彼此连接。 超绝缘板也可以设置在包括内部和外部衬里的壁中，该衬里被连接和密封以限定衬里之间的空间。 空间可以被抽真空并且可选地填充有超绝热气体。

公开(公告)号：US20050281988A1

公开(公告)日：2005-12-22

申请号：US11156890

申请日：2005-06-20

申请人： Bruce McCormick

发明人： Bruce McCormick

IPC分类号： A41D31/00 ,  A43B7/34 ,  A43B17/14 ,  B32B3/00

CPC分类号： B32B9/046 ,  A41D31/0038 ,  A43B7/34 ,  A43B17/14 ,  B32B3/04 ,  B32B5/18 ,  B32B5/22 ,  B32B2266/0235 ,  B32B2305/026 ,  B32B2307/304 ,  B32B2307/7242 ,  B32B2437/02 ,  Y10T428/2476

摘要： An insulating liner for an article of clothing includes a first layer, a second layer attached to the first layer, and an insulating layer sealed between the first and second layers, wherein the insulating layer is composed of an aerogel material. The first and second layers can be a PVC foam hermetically sealed about the aerogel material by welding. In a preferred embodiment, the insulating liner is a shoe liner that includes a polyester wearing material adhered to the top layer of PVC foam. A method of forming the insulating liner is also provided.

摘要翻译： 用于衣服的绝缘衬垫包括第一层，附着到第一层的第二层和密封在第一层和第二层之间的绝缘层，其中绝缘层由气凝胶材料构成。 第一层和第二层可以是通过焊接围绕气凝胶材料气密密封的PVC泡沫。 在一个优选实施例中，绝缘衬垫是鞋垫，其包括粘附到PVC泡沫的顶层的聚酯耐磨材料。 还提供了形成绝缘衬垫的方法。

公开(公告)号：US06196221B1

公开(公告)日：2001-03-06

申请号：US09246750

申请日：1999-02-08

申请人： Bruce McCormick

发明人： Bruce McCormick

IPC分类号： A61M1600

CPC分类号： A61M16/1045 ,  A61M16/06 ,  A61M16/0605 ,  A61M2205/0205

摘要： A thermal exchange breathing device is provided which include a heat exchange module 14 which is mounted in a face mask (12) with an air flow passage extending from a mouthpiece (72) through a breathing vent (64) to an atmospheric vent (68) through a heat exchange medium (68) in the heat exchange module. The face mask (12) is provided with a head strap (22,94) which may include connectors (95 and 95′) between the respective ends of the head strap and the sides of the face mask, said connectors including a stand-off (97) to keep the face mask snug against the user's face when the user wears a helmet.

摘要翻译： 提供一种热交换呼吸装置，其包括热交换模块14，该热交换模块14安装在面罩（12）中，空气流动通道从接口（72）延伸穿过呼吸通风口（64）到大气通风口（68） 通过热交换模块中的热交换介质（68）。 面罩（12）设置有头带（22,94），头带（22,94）可包括在头带的相应端部和面罩的侧面之间的连接器（95和95'），所述连接器包括支架 （97）当使用者佩戴头盔时，使面罩贴合使用者的脸部。

公开(公告)号：US5887285A

公开(公告)日：1999-03-30

申请号：US925570

申请日：1997-09-08

申请人： Bruce McCormick

发明人： Bruce McCormick

IPC分类号： A42C5/04 ,  A42C5/00

CPC分类号： A42C5/04

摘要： A headgear assembly including a flexible cap and an insulator adapted to increase the heat retention of the cap. The cap includes an interior surface and a peripheral edge which surround and define a hemispherical interior cavity. A sweatband is affixed to the peripheral edge of the cap and is located adjacent the interior surface of the cap. The insulator is disposed within the interior cavity of the cap and includes a peripheral edge disposed between the band and the interior surface of the cap which retains the insulator within the cap.