公开(公告)号：US08347068B2

公开(公告)日：2013-01-01

申请号：US11696363

申请日：2007-04-04

申请人： Richard James Eickemeyer ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Balaram Sinharoy

发明人： Richard James Eickemeyer ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Balaram Sinharoy

IPC分类号： G06F9/30

CPC分类号： G06F9/3851 ,  G06F9/30145 ,  G06F9/30189 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3857 ,  G06F9/3885

摘要： A multi-mode register rename mechanism which allows a simultaneous multi-threaded processor to support full out-of-order thread execution when the number of threads is low and in-order thread execution when the number of threads increases. Responsive to changing an execution mode of a processor to operate in in-order thread execution mode, the illustrative embodiments switch a physical register in the data processing system to an architected facility, thereby forming a switched physical register. When an instruction is issued to an execution unit, wherein the issued instruction comprises a thread bit, the thread bit is examined to determine if the instruction accesses an architected facility. If the issued instruction accesses an architected facility, the instruction is executed, and the results of the executed instruction are written to the switched physical register.

摘要翻译： 多模式寄存器重命名机制，允许同时多线程处理器在线程数量低时支持完全无序的线程执行，并且当线程数增加时按顺序执行线程。 响应于改变处理器的执行模式以按顺序执行线程执行模式，所述说明性实施例将数据处理系统中的物理寄存器切换到架构设施，从而形成切换的物理寄存器。 当向执行单元发出指令时，其中发出的指令包括一个线程位，检查该线程位以确定该指令是否访问一个架构设施。 如果发出的指令访问架构设施，则执行该指令，并且将所执行的指令的结果写入切换的物理寄存器。

公开(公告)号：US07827443B2

公开(公告)日：2010-11-02

申请号：US12270300

申请日：2008-11-13

申请人： Susan Elizabeth Eisen ,  Hung Qui Le ,  Michael James Mack ,  Dung Quoc Nguyen ,  Jose Angel Paredes ,  Scott Barnett Swaney

发明人： Susan Elizabeth Eisen ,  Hung Qui Le ,  Michael James Mack ,  Dung Quoc Nguyen ,  Jose Angel Paredes ,  Scott Barnett Swaney

IPC分类号： G06F11/00

CPC分类号： G06F12/0888 ,  G06F9/30043 ,  G06F9/3851 ,  G06F9/3863 ,  G06F11/1407

摘要： Recovery circuits react to errors in a processor core by waiting for an error-free completion of any pending store-conditional instruction or a cache-inhibited load before ceasing to checkpoint or backup progress of a processor core. Recovery circuits remove the processor core from the logical configuration of the symmetric multiprocessor system, potentially reducing propagation of errors to other parts of the system. The processor core is reset and the checkpointed values may be restored to registers of the processor core. The core processor is allowed not just to resume execution just prior to the instructions that failed to execute correctly the first time, but is allowed to operate in a reduced execution mode for a preprogrammed number of groups. If the preprogrammed number of instruction groups execute without error, the processor core is allowed to resume normal execution.

摘要翻译： 恢复电路通过在停止处理器核心的检查点或备份进程之前等待任何挂起的存储条件指令或高速缓存禁止负载的无差错完成来响应处理器内核中的错误。 恢复电路将处理器核从对称多处理器系统的逻辑配置中移除，可能会将错误的传播减少到系统的其他部分。 处理器内核被复位，检查点值可以恢复到处理器内核的寄存器。 允许核心处理器不仅在第一次执行失败的指令之前恢复执行，而且允许以预编程的组数减少执行模式运行。 如果指令组的预编程数量无错误地执行，则允许处理器内核恢复正常执行。

公开(公告)号：US07650486B2

公开(公告)日：2010-01-19

申请号：US12013572

申请日：2008-01-14

申请人： Hung Qui Le ,  Dung Quoc Nguyen ,  Brian William Thompto ,  Raymond Cheung Yeung

发明人： Hung Qui Le ,  Dung Quoc Nguyen ,  Brian William Thompto ,  Raymond Cheung Yeung

IPC分类号： G06F9/38

CPC分类号： G06F9/3851 ,  G06F9/3836

摘要： A method and apparatus for steering instructions dynamically, at issue time, so as to maximize the efficiency of use of execution units being shared by multiple threads being processed by an SMT processor. Resource vectors are used at issue time to redirect instructions, from threads being processed simultaneously, to shared resources for which the multiple threads are competing. The existing resource vectors for instructions that are queued for issuance are analyzed and, where appropriate, dynamically recalculated and modified for maximum efficiency.

摘要翻译： 一种用于在问题时刻动态地转向指令的方法和装置，以便最大化由SMT处理器处理的多个线程共享的执行单元的使用效率。 在发布时使用资源向量将来自正在被处理的线程的指令重定向到多个线程正在竞争的共享资源。 分析用于发行排队的指令的现有资源向量，并在适当情况下动态重新计算和修改以最大限度地提高效率。

公开(公告)号：US07478276B2

公开(公告)日：2009-01-13

申请号：US11054988

申请日：2005-02-10

申请人： James Wilson Bishop ,  Hung Qui Le ,  Michael James Mack ,  Jafar Nahidi ,  Dung Quoc Nguyen ,  Jose Angel Paredes ,  Scott Barnett Swaney ,  Brian William Thompto

发明人： James Wilson Bishop ,  Hung Qui Le ,  Michael James Mack ,  Jafar Nahidi ,  Dung Quoc Nguyen ,  Jose Angel Paredes ,  Scott Barnett Swaney ,  Brian William Thompto

IPC分类号： G06F11/00

CPC分类号： G06F11/1407

摘要： A method and apparatus are provided for dispatch group checkpointing in a microprocessor, including provisions for handling partially completed dispatch groups and instructions which modify system coherent state prior to completion. An instruction checkpoint retry mechanism is implemented to recover from soft errors in logic. The processor is able to dispatch fixed point unit (FXU), load/store unit (LSU), and floating point unit (FPU) or vector multimedia extension (VMX) instructions on the same cycle. Store data is written to a store queue when a store instruction finishes executing. The data is held in the store queue until the store instruction is checkpointed, at which point it can be released to the coherently shared level 2 (L2) cache.

摘要翻译： 提供了一种用于微处理器中的调度组检查点的方法和装置，包括用于处理部分完成的调度组的规定以及在完成之前修改系统相干状态的指令。 执行指令检查点重试机制以从逻辑中的软错误中恢复。 处理器能够在同一周期内调度固定点单元（FXU），加载/存储单元（LSU）和浮点单元（FPU）或矢量多媒体扩展（VMX）指令。 存储指令完成执行时，存储数据将写入存储队列。 数据保存在存储队列中，直到存储指令检查点为止，此时可将数据释放到相干共享的级别2（L2）缓存。

公开(公告)号：US07421567B2

公开(公告)日：2008-09-02

申请号：US11016206

申请日：2004-12-17

申请人： Richard James Eickemeyer ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Benjamin Walter Stolt ,  Brian William Thompto

发明人： Richard James Eickemeyer ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Benjamin Walter Stolt ,  Brian William Thompto

IPC分类号： G06F9/30 ,  G06F9/40 ,  G06F15/00

CPC分类号： G06F9/3842 ,  G06F9/3804 ,  G06F9/383 ,  G06F9/3838

摘要： The present invention allows a microprocessor to identify and speculatively execute future instructions during a stall condition. This allows forward progress to be made through the instruction stream during the stall condition which would otherwise cause the microprocessor or thread of execution to be idle. The execution of such future instructions can initiate a prefetch of data or instructions from a distant cache or main memory, or otherwise make forward progress through the instruction stream. In this manner, when the instructions are re-executed (non speculatively executed) after the stall condition expires, they will execute with a reduced execution latency; e.g. by accessing data prefetched into the L1 cache, or enroute to the processor, or by executing the target instructions following a speculatively resolved mispredicted branch. In speculative mode, instruction operands may be invalid due to source loads that miss the L1 cache, facilities not available in speculative execution mode, or due to speculative instruction results that are not available. Dependency and dirty (i.e. invalid result) bits are tracked and used to determine which speculative instructions are valid for execution. A modified value register storage and bit vector are used to improve the availability of speculative results that would otherwise be discarded once they leave the execution pipeline because they cannot be written to the architected registers. The modified general purpose registers are used to store speculative results when the corresponding instruction reaches writeback and the modified bit vector tracks the results that have been stored there. Younger speculative instructions that do not bypass directly from older instructions will then use this modified data when the corresponding bit in the modified bit vector indicates the data has been modified. Otherwise, data from the architected registers will be used.

摘要翻译： 本发明允许微处理器在失速状态期间识别和推测地执行未来的指令。 这允许在停顿条件期间通过指令流进行正向进展，否则将导致微处理器或执行线程空闲。 这样的未来指令的执行可以启动来自远程高速缓存或主存储器的数据或指令的预取，或以其他方式通过指令流进行进展。 以这种方式，当在停止条件到期之后重新执行（不推测地执行）指令时，它们将以降低的执行延迟执行; 例如 通过访问预取到L1高速缓存中的数据，或者进入处理器，或通过在推测性地解决的误预测分支之后执行目标指令。 在推测模式中，由于缺少L1缓存的源加载，在推测执行模式下不可用的设备，或由于不可用的推测指令结果，指令操作数可能无效。 跟踪依赖关系和脏（即无效结果）位，并用于确定哪些推测指令对执行有效。 改进的值寄存器存储和位向量被用于提高推测结果的可用性，否则，由于不能将其写入到架构化的寄存器，否则将抛弃执行流水线。 修改后的通用寄存器用于在对应指令到达回写时存储推测结果，修改后的位向量跟踪存储在其中的结果。 当修改的位向量中的相应位指示数据已被修改时，不直接从旧指令旁路的较小的推测指令将使用该修改的数据。 否则，将使用来自架构化寄存器的数据。

公开(公告)号：US07302553B2

公开(公告)日：2007-11-27

申请号：US10351556

申请日：2003-01-23

申请人： Sam Gat-Shang Chu ,  Hung Qui Le ,  Dung Quoc Nguyen

发明人： Sam Gat-Shang Chu ,  Hung Qui Le ,  Dung Quoc Nguyen

IPC分类号： G06F9/30 ,  G06F9/40 ,  G06F15/00

CPC分类号： G06F9/3836 ,  G06F9/3855 ,  G06F9/3857

摘要： An apparatus, system and method for quickly determining an oldest instruction in a non-moving instruction queue of a processor are provided. Particularly, instructions are stored, one at a time at a clock cycle, in the non-moving queue. At every clock cycle, a present status of the instructions in the queue is recorded. Using the present status of the instructions in the queue in conjunction with previously recorded statuses of the instructions, the oldest instruction in the queue is determined. The status of the instructions in the queue includes whether or not the instruction has been issued for execution as well as whether or not it is known that the issued instruction has been accepted for execution.

摘要翻译： 提供了一种用于快速确定处理器的非移动指令队列中的最旧指令的装置，系统和方法。 特别地，在不移动队列中，以时钟周期一次存储指令。 在每个时钟周期，记录队列中的指令的当前状态。 结合队列中的指令的当前状态结合先前记录的指令状态，确定队列中最早的指令。 队列中的指令的状态包括是否已经发出指令执行，以及是否知道发出的指令已被接受执行。

公开(公告)号：US07237094B2

公开(公告)日：2007-06-26

申请号：US10965143

申请日：2004-10-14

申请人： Brian William Curran ,  Brian R. Konigsburg ,  Hung Qui Le ,  David Arnold Luick ,  Dung Quoc Nguyen

发明人： Brian William Curran ,  Brian R. Konigsburg ,  Hung Qui Le ,  David Arnold Luick ,  Dung Quoc Nguyen

IPC分类号： G06F9/38

CPC分类号： G06F9/3853 ,  G06F9/30145 ,  G06F9/382 ,  G06F9/3851 ,  G06F9/3885

摘要： A more efficient method of handling instructions in a computer processor, by associating resource fields with respective program instructions wherein the resource fields indicate which of the processor hardware resources are required to carry out the program instructions, calculating resource requirements for merging two or more program instructions based on their resource fields, and determining resource availability for simultaneously executing the merged program instructions based on the calculated resource requirements. Resource vectors indicative of the required resource may be encoded into the resource fields, and the resource fields decoded at a later stage to derive the resource vectors. The resource fields can be stored in the instruction cache associated with the respective program instructions. The processor may operate in a simultaneous multithreading mode with different program instructions being part of different hardware threads. When the resource availability equals or exceeds the resource requirements for a group of instructions, those instructions can be dispatched simultaneously to the hardware resources. A start bit may be inserted in one of the program instructions to define the instruction group. The hardware resources may in particular be execution units such as a fixed-point unit, a load/store unit, a floating-point unit, or a branch processing unit.

摘要翻译： 通过将资源字段与相应的程序指令相关联来处理计算机处理器中的指令的更有效的方法，其中资源字段指示需要哪个处理器硬件资源来执行程序指令，计算用于合并两个或多个程序指令的资源需求 并且基于所计算的资源需求来确定用于同时执行所合并的程序指令的资源可用性。 指示所需资源的资源矢量可以被编码到资源字段中，并且在稍后阶段解码资源字段以导出资源向量。 资源字段可以存储在与相应的程序指令相关联的指令高速缓存中。 处理器可以以同时多线程模式操作，其中不同的程序指令是不同硬件线程的一部分。 当资源可用性等于或超过一组指令的资源需求时，可以将这些指令同时发送到硬件资源。 可以在程序指令之一中插入起始位以定义指令组。 硬件资源可以特别地是诸如定点单元，加载/存储单元，浮点单元或分支处理单元之类的执行单元。

公开(公告)号：US08418180B2

公开(公告)日：2013-04-09

申请号：US12129876

申请日：2008-05-30

申请人： James Wilson Bishop ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Balaram Sinharoy ,  Brian William Thompto ,  Raymond Cheung Yeung

发明人： James Wilson Bishop ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Balaram Sinharoy ,  Brian William Thompto ,  Raymond Cheung Yeung

IPC分类号： G06F9/46

CPC分类号： G06F9/30101 ,  G06F9/3834 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/3885 ,  G06F9/4818 ,  G06F9/485

摘要： A method, apparatus, and computer program product are disclosed for ensuring processing fairness in simultaneous multi-threading (SMT) microprocessors. A clock cycle priority is assigned to a first thread and to a second thread during a standard selection state that lasts for an expected number of clock cycles by selecting the first thread to be a primary thread and the second thread to be a secondary thread. If a condition exists that requires overriding, an override state is executed by selecting the second thread to be the primary thread and the first thread to be the secondary thread. The override state is forced to be executed for an override period of time which equals the expected number of clock cycles plus a forced number of clock cycles. The forced number of clock cycles is granted to the first thread in response to the first thread again becoming the primary thread.

摘要翻译： 公开了一种用于确保同时多线程（SMT）微处理器中的处理公平性的方法，装置和计算机程序产品。 在通过选择作为主线程的第一线程和第二线程成为辅线程的持续期望的时钟周期数的标准选择状态期间，将时钟周期优先级分配给第一线程和第二线程。 如果存在需要覆盖的条件，则通过选择作为主线程的第二个线程和第一个线程作为辅助线程来执行覆盖状态。 超时状态被强制执行超时时间等于预期的时钟周期数加上强制的时钟周期数。 响应于第一个线程再次成为主线程，强制的时钟周期数被授予第一个线程。

公开(公告)号：US20090063898A1

公开(公告)日：2009-03-05

申请号：US12270300

申请日：2008-11-13

申请人： Susan Elizabeth Eisen ,  Hung Qui Le ,  Michael James Mack ,  Dung Quoc Nguyen ,  Jose Angel Paredes ,  Scott Barnett Swaney

发明人： Susan Elizabeth Eisen ,  Hung Qui Le ,  Michael James Mack ,  Dung Quoc Nguyen ,  Jose Angel Paredes ,  Scott Barnett Swaney

IPC分类号： G06F11/20

CPC分类号： G06F12/0888 ,  G06F9/30043 ,  G06F9/3851 ,  G06F9/3863 ,  G06F11/1407

摘要： Recovery circuits react to errors in a processor core by waiting for an error-free completion of any pending store-conditional instruction or a cache-inhibited load before ceasing to checkpoint or backup progress of a processor core. Recovery circuits remove the processor core from the logical configuration of the symmetric multiprocessor system, potentially reducing propagation of errors to other parts of the system. The processor core is reset and the checkpointed values may be restored to registers of the processor core. The core processor is allowed not just to resume execution just prior to the instructions that failed to execute correctly the first time, but is allowed to operate in a reduced execution mode for a preprogrammed number of groups. If the preprogrammed number of instruction groups execute without error, the processor core is allowed to resume normal execution.

摘要翻译： 恢复电路通过在停止处理器核心的检查点或备份进程之前等待任何挂起的存储条件指令或高速缓存禁止负载的无差错完成来响应处理器内核中的错误。 恢复电路将处理器核从对称多处理器系统的逻辑配置中移除，可能会将错误的传播减少到系统的其他部分。 处理器内核被复位，检查点值可以恢复到处理器内核的寄存器。 允许核心处理器不仅在第一次执行失败的指令之前恢复执行，而且允许以预编程的组数减少执行模式运行。 如果指令组的预编程数量无错误地执行，则允许处理器内核恢复正常执行。

公开(公告)号：US07490226B2

公开(公告)日：2009-02-10

申请号：US11054289

申请日：2005-02-09

申请人： Hung Qui Le ,  Dung Quoc Nguyen ,  Raymond Cheung Yeung

发明人： Hung Qui Le ,  Dung Quoc Nguyen ,  Raymond Cheung Yeung

IPC分类号： G06F9/312

CPC分类号： G06F9/383 ,  G06F9/3834 ,  G06F9/3838 ,  G06F9/3867

摘要： A method and related apparatus is provided for a processor having a number of registers, wherein instructions are sequentially issued to move through a sequence of execution stages, from an initial stage to a final write back stage. As a method, an embodiment includes the step of issuing a first instruction, such as an FMA instruction, to move through the sequence of execution stages, the first instruction being directed to a specified one of the registers. The method further includes issuing a second instruction to move through the execution stages, the second instruction being issued after the first instruction has issued, but before the first instruction reaches the final write back stage. The second instruction is likewise directed to the specified register, and comprises either a store instruction or a load instruction, selectively. R and W bits corresponding to the specified register are used to ensure that a store instruction does not read data from, and that a load instruction does not write data to the specified register, respectively, before the first instruction is moved to the final write back stage.

摘要翻译： 提供了一种用于具有多个寄存器的处理器的方法和相关装置，其中顺序地发出指令以从初始阶段到最终回写阶段移动经过一系列执行阶段。 作为一种方法，实施例包括发出诸如FMA指令的第一指令以移动经过执行级序列的步骤，第一指令被引导到指定的一个寄存器。 该方法还包括发出第二指令以移动通过执行阶段，第二指令在第一指令发出之后但在第一指令到达最终回写阶段之前发出。 第二条指令同样针对指定的寄存器，并且选择性地包括存储指令或加载指令。 使用与指定寄存器相对应的R和W位来确保存储指令不会从第一指令移动到最终回写之前分别读取数据，并且加载指令不会将数据写入指定的寄存器 阶段。